From 3744a7febb51ac3e62ad305e0fa43c17d5142474 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 7 Dec 2011 23:01:10 +0000 Subject: [PATCH] ARM two-operand aliases for VADDW instructions. llvm-svn: 146093 --- llvm/lib/Target/ARM/ARMInstrNEON.td | 14 ++++++++++++++ llvm/test/MC/ARM/neon-add-encoding.s | 17 +++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 4828f3a844a0..11c8e0b79124 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -5321,6 +5321,20 @@ def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm", def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm", (VADDfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; +// VADDW two-operand aliases. +def : NEONInstAlias<"vaddw${p}.s8 $Vdn, $Vm", + (VADDWsv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>; +def : NEONInstAlias<"vaddw${p}.s16 $Vdn, $Vm", + (VADDWsv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>; +def : NEONInstAlias<"vaddw${p}.s32 $Vdn, $Vm", + (VADDWsv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>; +def : NEONInstAlias<"vaddw${p}.u8 $Vdn, $Vm", + (VADDWuv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>; +def : NEONInstAlias<"vaddw${p}.u16 $Vdn, $Vm", + (VADDWuv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>; +def : NEONInstAlias<"vaddw${p}.u32 $Vdn, $Vm", + (VADDWuv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>; + // VAND/VEOR/VORR accept but do not require a type suffix. defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm", (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; diff --git a/llvm/test/MC/ARM/neon-add-encoding.s b/llvm/test/MC/ARM/neon-add-encoding.s index fb5c7e1d3fcd..19d5b7e010f7 100644 --- a/llvm/test/MC/ARM/neon-add-encoding.s +++ b/llvm/test/MC/ARM/neon-add-encoding.s @@ -158,3 +158,20 @@ @ CHECK: vadd.i16 q7, q7, q1 @ encoding: [0x42,0xe8,0x1e,0xf2] @ CHECK: vadd.i32 q8, q8, q2 @ encoding: [0xc4,0x08,0x60,0xf2] @ CHECK: vadd.i64 q9, q9, q3 @ encoding: [0xc6,0x28,0x72,0xf2] + + + vaddw.s8 q6, d5 + vaddw.s16 q7, d1 + vaddw.s32 q8, d2 + + vaddw.u8 q6, d5 + vaddw.u16 q7, d1 + vaddw.u32 q8, d2 + +@ CHECK: vaddw.s8 q6, q6, d5 @ encoding: [0x05,0xc1,0x8c,0xf2] +@ CHECK: vaddw.s16 q7, q7, d1 @ encoding: [0x01,0xe1,0x9e,0xf2] +@ CHECK: vaddw.s32 q8, q8, d2 @ encoding: [0x82,0x01,0xe0,0xf2] + +@ CHECK: vaddw.u8 q6, q6, d5 @ encoding: [0x05,0xc1,0x8c,0xf3] +@ CHECK: vaddw.u16 q7, q7, d1 @ encoding: [0x01,0xe1,0x9e,0xf3] +@ CHECK: vaddw.u32 q8, q8, d2 @ encoding: [0x82,0x01,0xe0,0xf3]