Improve handling of COPY instructions with identical value numbers
Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 334594
This commit is contained in:
Krzysztof Parzyszek
parent
3957e48a68
commit
36b816f814
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@ -2085,9 +2085,24 @@ class JoinVals {
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LaneBitmask computeWriteLanes(const MachineInstr *DefMI, bool &Redef) const;
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/// Find the ultimate value that VNI was copied from.
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std::pair<const VNInfo*,unsigned> followCopyChain(const VNInfo *VNI) const;
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std::tuple<const VNInfo*,unsigned, bool>
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followCopyChain(const VNInfo *VNI, unsigned OtherReg) const;
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bool valuesIdentical(VNInfo *Val0, VNInfo *Val1, const JoinVals &Other) const;
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/// Determine whether Val0 for Reg and Val1 for Other.Reg are identical.
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/// The first element of the returned pair is true if they are, false
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/// otherwise. The second element is true if one value is defined
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/// directly via the other, e.g.:
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/// %reg0 = ...
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/// %regx = COPY %reg0 ;; reg1 defined via reg0
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/// %reg1 = COPY %regx ;; val0 == val1
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/// -> { true, true }
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/// vs
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/// %reg0 = COPY %regy
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/// %regx = COPY %regy
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/// $reg1 = COPY %regx ;; val0 == val1
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/// -> { true, false }
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std::pair<bool,bool> valuesIdentical(VNInfo *Val0, VNInfo *Val1,
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const JoinVals &Other) const;
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/// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
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/// Return a conflict resolution when possible, but leave the hard cases as
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@ -2203,19 +2218,22 @@ LaneBitmask JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
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return L;
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}
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std::pair<const VNInfo*, unsigned> JoinVals::followCopyChain(
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const VNInfo *VNI) const {
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std::tuple<const VNInfo*, unsigned, bool> JoinVals::followCopyChain(
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const VNInfo *VNI, unsigned OtherReg) const {
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unsigned Reg = this->Reg;
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bool UsedOtherReg = false;
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while (!VNI->isPHIDef()) {
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SlotIndex Def = VNI->def;
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MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
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assert(MI && "No defining instruction");
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if (!MI->isFullCopy())
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return std::make_pair(VNI, Reg);
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return std::make_tuple(VNI, Reg, UsedOtherReg);
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unsigned SrcReg = MI->getOperand(1).getReg();
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if (SrcReg == OtherReg)
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UsedOtherReg = true;
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if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
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return std::make_pair(VNI, Reg);
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return std::make_tuple(VNI, Reg, UsedOtherReg);
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const LiveInterval &LI = LIS->getInterval(SrcReg);
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const VNInfo *ValueIn;
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@ -2241,26 +2259,28 @@ std::pair<const VNInfo*, unsigned> JoinVals::followCopyChain(
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VNI = ValueIn;
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Reg = SrcReg;
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}
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return std::make_pair(VNI, Reg);
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return std::make_tuple(VNI, Reg, UsedOtherReg);
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}
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bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
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const JoinVals &Other) const {
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std::pair<bool,bool> JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
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const JoinVals &Other) const {
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const VNInfo *Orig0;
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unsigned Reg0;
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std::tie(Orig0, Reg0) = followCopyChain(Value0);
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if (Orig0 == Value1)
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return true;
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bool Other0;
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std::tie(Orig0, Reg0, Other0) = followCopyChain(Value0, Other.Reg);
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if (Orig0 == Value1 && Reg0 == Other.Reg)
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return std::make_pair(true, Other0);
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const VNInfo *Orig1;
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unsigned Reg1;
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std::tie(Orig1, Reg1) = Other.followCopyChain(Value1);
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bool Other1;
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std::tie(Orig1, Reg1, Other1) = Other.followCopyChain(Value1, Reg);
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// The values are equal if they are defined at the same place and use the
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// same register. Note that we cannot compare VNInfos directly as some of
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// them might be from a copy created in mergeSubRangeInto() while the other
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// is from the original LiveInterval.
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return Orig0->def == Orig1->def && Reg0 == Reg1;
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return std::make_pair(Orig0->def == Orig1->def && Reg0 == Reg1, Other1);
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}
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JoinVals::ConflictResolution
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@ -2430,9 +2450,22 @@ JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
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// %other = COPY %ext
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// %this = COPY %ext <-- Erase this copy
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//
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if (DefMI->isFullCopy() && !CP.isPartial()
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&& valuesIdentical(VNI, V.OtherVNI, Other))
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return CR_Erase;
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// One case to be careful about is a case where the travesal of the
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// COPY chain for one register encounters a use of the other register,
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// e.g.
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// 10 %other = COPY ...
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// 20 %x = COPY %other
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// 30 %this = COPY %x ;; assume that liveness of %this extends to the
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// ;; end of the block (then back to the entry phi)
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// Coalescing %this and %other can force a gap in the live range between
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// 20r and 30r, and if the COPY at 30 is erased, its liveness will no longer
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// extend to the end of the block (an IMPLICIT_DEF may incorrectly be added
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// later on to create a definition that is live on exit).
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if (DefMI->isFullCopy() && !CP.isPartial()) {
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std::pair<bool,bool> P = valuesIdentical(VNI, V.OtherVNI, Other);
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if (P.first)
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return P.second ? CR_Merge : CR_Erase;
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}
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// If the lanes written by this instruction were all undef in OtherVNI, it is
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// still safe to join the live ranges. This can't be done with a simple value
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@ -2957,7 +2990,8 @@ void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
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LRange.join(RRange, LHSVals.getAssignments(), RHSVals.getAssignments(),
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NewVNInfo);
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LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << LRange << "\n");
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LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << PrintLaneMask(LaneMask) << ' '
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<< LRange << "\n");
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if (EndPoints.empty())
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return;
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@ -0,0 +1,215 @@
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# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing,rename-independent-subregs %s -o - | FileCheck -check-prefix=GCN %s
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# This test is for a bug where the following happens:
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#
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# Inside the loop, %29.sub2 is used in a V_LSHLREV whose result is then used
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# in an LDS read. %29 is a 128 bit value that is linked by copies to
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# %45 (from phi elimination), %28 (the value in the loop pre-header),
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# %31 (defined and subreg-modified in the loop, and used after the loop)
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# and %30:
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#
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# %45:vreg_128 = COPY killed %28
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# bb.39:
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# %29:vreg_128 = COPY killed %45
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# %39:vgpr_32 = V_LSHLREV_B32_e32 2, %29.sub2, implicit $exec
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# %31:vreg_128 = COPY killed %29
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# %31.sub1:vreg_128 = COPY %34
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# %30:vreg_128 = COPY %31
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# %45:vreg_128 = COPY killed %30
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# S_CBRANCH_EXECNZ %bb.39, implicit $exec
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# S_BRANCH %bb.40
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# bb.40:
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# undef %8615.sub0:vreg_128 = COPY killed %31.sub0
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#
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# So this coalesces together into a single 128 bit value whose sub1 is modified
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# in the loop, but the sub2 used in the V_LSHLREV is not modified in the loop.
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#
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# The bug is that the coalesced value has a L00000004 subrange (for sub2) that
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# says that it is not live up to the end of the loop block. The symptom is that
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# Rename Independent Subregs separates sub2 into its own register, and it is
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# not live round the loop, so that pass adds an IMPLICIT_DEF for it just before
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# the loop backedge.
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# GCN: bb.1 (%ir-block.6):
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# GCN: V_LSHLREV_B32_e32 2, [[val:%[0-9][0-9]*]].sub2
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# GCN-NOT: [[val]]:vreg_128 = IMPLICIT_DEF
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--- |
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
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target triple = "amdgcn--amdpal"
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define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32>) local_unnamed_addr #0 {
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.entry:
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br label %6
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; <label>:6: ; preds = %6, %.entry
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%7 = bitcast i32 addrspace(3)* undef to <2 x i32> addrspace(3)*
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%8 = bitcast i32 addrspace(3)* undef to <2 x i32> addrspace(3)*
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%9 = bitcast i32 addrspace(3)* undef to <2 x i32> addrspace(3)*
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%10 = bitcast i32 addrspace(3)* undef to <2 x i32> addrspace(3)*
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%11 = bitcast i32 addrspace(3)* undef to <2 x i32> addrspace(3)*
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%12 = bitcast i32 addrspace(3)* undef to <2 x i32> addrspace(3)*
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br i1 undef, label %13, label %6
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; <label>:13: ; preds = %6
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ret void
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}
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attributes #0 = { "target-cpu"="gfx803" }
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...
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---
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name: _amdgpu_cs_main
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_64, preferred-register: '' }
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- { id: 1, class: sreg_64, preferred-register: '' }
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- { id: 2, class: sreg_64, preferred-register: '' }
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- { id: 3, class: sgpr_32, preferred-register: '' }
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- { id: 4, class: sgpr_32, preferred-register: '' }
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- { id: 5, class: sgpr_32, preferred-register: '' }
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- { id: 6, class: sgpr_32, preferred-register: '' }
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- { id: 7, class: sreg_32_xm0, preferred-register: '' }
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- { id: 8, class: sgpr_32, preferred-register: '' }
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- { id: 9, class: sreg_32_xm0, preferred-register: '' }
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- { id: 10, class: sreg_32_xm0, preferred-register: '' }
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- { id: 11, class: sreg_32_xm0, preferred-register: '' }
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- { id: 12, class: vreg_64, preferred-register: '' }
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- { id: 13, class: vreg_64, preferred-register: '' }
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- { id: 14, class: vreg_64, preferred-register: '' }
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- { id: 15, class: vreg_64, preferred-register: '' }
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- { id: 16, class: vreg_64, preferred-register: '' }
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- { id: 17, class: vreg_64, preferred-register: '' }
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- { id: 18, class: sreg_64, preferred-register: '$vcc' }
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- { id: 19, class: vreg_128, preferred-register: '' }
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- { id: 20, class: vreg_128, preferred-register: '' }
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- { id: 21, class: vreg_128, preferred-register: '' }
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- { id: 22, class: vreg_128, preferred-register: '' }
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- { id: 23, class: vreg_128, preferred-register: '' }
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- { id: 24, class: vreg_128, preferred-register: '' }
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- { id: 25, class: vreg_128, preferred-register: '' }
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- { id: 26, class: vreg_128, preferred-register: '' }
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- { id: 27, class: vreg_128, preferred-register: '' }
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- { id: 28, class: vreg_128, preferred-register: '' }
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- { id: 29, class: vreg_128, preferred-register: '' }
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- { id: 30, class: vreg_128, preferred-register: '' }
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- { id: 31, class: vreg_128, preferred-register: '' }
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- { id: 32, class: vreg_128, preferred-register: '' }
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- { id: 33, class: vgpr_32, preferred-register: '' }
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- { id: 34, class: sreg_32, preferred-register: '' }
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- { id: 35, class: vreg_128, preferred-register: '' }
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- { id: 36, class: vreg_128, preferred-register: '' }
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- { id: 37, class: vreg_128, preferred-register: '' }
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- { id: 38, class: vgpr_32, preferred-register: '' }
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- { id: 39, class: vgpr_32, preferred-register: '' }
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- { id: 40, class: vgpr_32, preferred-register: '' }
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- { id: 41, class: vgpr_32, preferred-register: '' }
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- { id: 42, class: vreg_128, preferred-register: '' }
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- { id: 43, class: sreg_64, preferred-register: '' }
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- { id: 44, class: vreg_128, preferred-register: '' }
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- { id: 45, class: vreg_128, preferred-register: '' }
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liveins:
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0..entry:
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successors: %bb.1(0x80000000)
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%3:sgpr_32 = S_MOV_B32 0
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undef %19.sub1:vreg_128 = COPY undef %3
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dead %4:sgpr_32 = S_MOV_B32 1
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%20:vreg_128 = COPY killed %19
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%20.sub1:vreg_128 = COPY undef %4
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dead %5:sgpr_32 = S_MOV_B32 2
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%21:vreg_128 = COPY killed %20
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%21.sub1:vreg_128 = COPY undef %5
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dead %6:sgpr_32 = S_MOV_B32 3
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%22:vreg_128 = COPY killed %21
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%22.sub1:vreg_128 = COPY undef %6
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dead %7:sreg_32_xm0 = S_MOV_B32 4
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%23:vreg_128 = COPY killed %22
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%23.sub1:vreg_128 = COPY undef %7
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dead %8:sgpr_32 = S_MOV_B32 5
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%24:vreg_128 = COPY killed %23
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%24.sub1:vreg_128 = COPY undef %8
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dead %9:sreg_32_xm0 = S_MOV_B32 6
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%25:vreg_128 = COPY killed %24
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%25.sub1:vreg_128 = COPY undef %9
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dead %10:sreg_32_xm0 = S_MOV_B32 7
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%26:vreg_128 = COPY killed %25
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%26.sub1:vreg_128 = COPY undef %10
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%11:sreg_32_xm0 = S_MOV_B32 255
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%27:vreg_128 = COPY killed %26
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%27.sub1:vreg_128 = COPY %11
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%28:vreg_128 = COPY killed %27
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%28.sub2:vreg_128 = COPY killed %11
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%2:sreg_64 = S_MOV_B64 0
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%34:sreg_32 = S_MOV_B32 7
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%37:vreg_128 = COPY undef %42:vreg_128
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%43:sreg_64 = COPY killed %2
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%44:vreg_128 = COPY killed %37
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%45:vreg_128 = COPY killed %28
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bb.1 (%ir-block.6):
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successors: %bb.2(0x04000000), %bb.1(0x7c000000)
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%29:vreg_128 = COPY killed %45
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%36:vreg_128 = COPY killed %44
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%0:sreg_64 = COPY killed %43
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%39:vgpr_32 = V_LSHLREV_B32_e32 2, %29.sub2, implicit $exec
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%41:vgpr_32 = V_ADD_I32_e32 1152, %39, implicit-def dead $vcc, implicit $exec
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$m0 = S_MOV_B32 -1
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%12:vreg_64 = DS_READ2_B32 killed %41, 0, 1, 0, implicit $m0, implicit $exec :: (load 8 from %ir.7, align 4, addrspace 3)
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%13:vreg_64 = DS_READ2_B32 %39, -112, -111, 0, implicit $m0, implicit $exec :: (load 8 from %ir.8, align 4, addrspace 3)
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%14:vreg_64 = DS_READ2_B32 %39, 0, 1, 0, implicit $m0, implicit $exec :: (load 8 from %ir.9, align 4, addrspace 3)
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%40:vgpr_32 = V_ADD_I32_e32 1160, %39, implicit-def dead $vcc, implicit $exec
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%15:vreg_64 = DS_READ2_B32 killed %40, 0, 1, 0, implicit $m0, implicit $exec :: (load 8 from %ir.10, align 4, addrspace 3)
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%16:vreg_64 = DS_READ2_B32 %39, -110, -109, 0, implicit $m0, implicit $exec :: (load 8 from %ir.11, align 4, addrspace 3)
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%17:vreg_64 = DS_READ2_B32 %39, 2, 3, 0, implicit $m0, implicit $exec :: (load 8 from %ir.12, align 4, addrspace 3)
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undef %35.sub1:vreg_128 = COPY undef %34
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%31:vreg_128 = COPY killed %29
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%31.sub1:vreg_128 = COPY %34
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%38:vgpr_32 = V_ADD_I32_e32 1, %36.sub0, implicit-def dead $vcc, implicit $exec
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%18:sreg_64 = V_CMP_LT_I32_e64 5, %38, implicit $exec
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%1:sreg_64 = S_OR_B64 killed %18, killed %0, implicit-def $scc
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%30:vreg_128 = COPY %31
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%43:sreg_64 = COPY %1
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%44:vreg_128 = COPY %35
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%45:vreg_128 = COPY killed %30
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$exec = S_ANDN2_B64_term $exec, %1
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S_CBRANCH_EXECNZ %bb.1, implicit $exec
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S_BRANCH %bb.2
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bb.2 (%ir-block.13):
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$exec = S_OR_B64 $exec, killed %1, implicit-def $scc
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%33:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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undef %32.sub0:vreg_128 = COPY killed %31.sub0
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%32.sub2:vreg_128 = COPY %33
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S_ENDPGM
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...
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