replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

t2Bcc is allowed to have a predicate without a preceding IT instruction. 

llvm-svn: 138946
This commit is contained in:
Owen Anderson 2011-09-01 17:47:45 +00:00
parent e417273fce
commit 35d240f9e8
2 changed files with 8 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -3377,7 +3377,8 @@ validateInstruction(MCInst &Inst,
// Check for non-'al' condition codes outside of the IT block. // Check for non-'al' condition codes outside of the IT block.
} else if (isThumbTwo() && MCID.isPredicable() && } else if (isThumbTwo() && MCID.isPredicable() &&
Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
ARMCC::AL && Inst.getOpcode() != ARM::tBcc) ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
Inst.getOpcode() != ARM::t2Bcc)
return Error(Loc, "predicated instructions must be in IT block"); return Error(Loc, "predicated instructions must be in IT block");
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {

6
llvm/test/MC/ARM/basic-thumb2-instructions.s
View File

@ -86,6 +86,12 @@ _func:
@ CHECK: addw r12, r6, #256 @ encoding: [0x06,0xf2,0x00,0x1c] @ CHECK: addw r12, r6, #256 @ encoding: [0x06,0xf2,0x00,0x1c]
@ CHECK: adds.w r1, r2, #496 @ encoding: [0x12,0xf5,0xf8,0x71] @ CHECK: adds.w r1, r2, #496 @ encoding: [0x12,0xf5,0xf8,0x71]
@------------------------------------------------------------------------------
@ B
@------------------------------------------------------------------------------
bmi.w #-183396
@ CHECK: bmi.w #-183396 @ encoding: [0x13,0xf5,0xce,0xa9]
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------
@ CBZ/CBNZ @ CBZ/CBNZ