reenable collapse of loadimm+AND -> dep.z (thanks guys)
llvm-svn: 22944
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@ -1439,7 +1439,7 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
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case MVT::i32:
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case MVT::i64: {
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Tmp1 = SelectExpr(N.getOperand(0));
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/* FIXME switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
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switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
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case 1: // ANDing a constant that is 2^n-1 for some n
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switch (Tmp3) {
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case 8: // if AND 0x00000000000000FF, be quaint and use zxt1
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@ -1452,12 +1452,13 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
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BuildMI(BB, IA64::ZXT4, 1, Result).addReg(Tmp1);
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break;
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default: // otherwise, use dep.z to paste zeros
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BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
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// FIXME: assert the dep.z is in bounds
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BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
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.addImm(0).addImm(Tmp3);
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break;
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}
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return Result; // early exit
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FIXME } */ // fallthrough and emit a simple AND:
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}
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return Result; // early exit
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} // fallthrough and emit a simple AND:
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, IA64::AND, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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