Add out of line virtual destructors to all LLVMTargetMachine subclasses

These recently all grew a unique_ptr<TargetLoweringObjectFile> member in
r221878.  When anyone calls a virtual method of a class, clang-cl
requires all virtual methods to be semantically valid. This includes the
implicit virtual destructor, which triggers instantiation of the
unique_ptr destructor, which fails because the type being deleted is
incomplete.

This is just part of the ongoing saga of PR20337, which is affecting
Blink as well. Because the MSVC ABI doesn't have key functions, we end
up referencing the vtable and implicit destructor on any virtual call
through a class. We don't actually end up emitting the dtor, so it'd be
good if we could avoid this unneeded type completion work.

llvm-svn: 222480

llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

@@ -117,6 +117,8 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
   initAsmInfo();
 }
 
+AArch64TargetMachine::~AArch64TargetMachine() {}
+
 const AArch64Subtarget *
 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
   AttributeSet FnAttrs = F.getAttributes();

llvm/lib/Target/AArch64/AArch64TargetMachine.h

@@ -33,6 +33,8 @@ public:
                        Reloc::Model RM, CodeModel::Model CM,
                        CodeGenOpt::Level OL, bool IsLittleEndian);
 
+  ~AArch64TargetMachine() override;
+
   const AArch64Subtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }

llvm/lib/Target/ARM/ARMTargetMachine.cpp

@@ -69,6 +69,8 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
         Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
 }
 
+ARMBaseTargetMachine::~ARMBaseTargetMachine() {}
+
 const ARMSubtarget *
 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
   AttributeSet FnAttrs = F.getAttributes();

llvm/lib/Target/ARM/ARMTargetMachine.h

@@ -35,6 +35,7 @@ public:
                        Reloc::Model RM, CodeModel::Model CM,
                        CodeGenOpt::Level OL,
                        bool isLittle);
+  ~ARMBaseTargetMachine() override;
 
   const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
   const ARMSubtarget *getSubtargetImpl(const Function &F) const override;

llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp

@@ -75,6 +75,8 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
     initAsmInfo();
 }
 
+HexagonTargetMachine::~HexagonTargetMachine() {}
+
 namespace {
 /// Hexagon Code Generator Pass Configuration Options.
 class HexagonPassConfig : public TargetPassConfig {

llvm/lib/Target/Hexagon/HexagonTargetMachine.h

@@ -31,6 +31,7 @@ public:
                        StringRef FS, const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
                        CodeGenOpt::Level OL);
+  ~HexagonTargetMachine() override;
 
   const HexagonSubtarget *getSubtargetImpl() const override {
     return &Subtarget;

llvm/lib/Target/MSP430/MSP430TargetMachine.cpp

@@ -36,6 +36,8 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, StringRef TT,
   initAsmInfo();
 }
 
+MSP430TargetMachine::~MSP430TargetMachine() {}
+
 namespace {
 /// MSP430 Code Generator Pass Configuration Options.
 class MSP430PassConfig : public TargetPassConfig {

llvm/lib/Target/MSP430/MSP430TargetMachine.h

@@ -32,6 +32,7 @@ public:
                       StringRef CPU, StringRef FS, const TargetOptions &Options,
                       Reloc::Model RM, CodeModel::Model CM,
                       CodeGenOpt::Level OL);
+  ~MSP430TargetMachine() override;
 
   const MSP430Subtarget *getSubtargetImpl() const override {
     return &Subtarget;

llvm/lib/Target/Mips/MipsTargetMachine.cpp

@@ -69,6 +69,8 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
   initAsmInfo();
 }
 
+MipsTargetMachine::~MipsTargetMachine() {}
+
 void MipsebTargetMachine::anchor() { }
 
 MipsebTargetMachine::

llvm/lib/Target/Mips/MipsTargetMachine.h

@@ -38,6 +38,7 @@ public:
   MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
                     const TargetOptions &Options, Reloc::Model RM,
                     CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
+  ~MipsTargetMachine() override;
 
   void addAnalysisPasses(PassManagerBase &PM) override;
 

llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp

@@ -80,6 +80,8 @@ NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
   initAsmInfo();
 }
 
+NVPTXTargetMachine::~NVPTXTargetMachine() {}
+
 void NVPTXTargetMachine32::anchor() {}
 
 NVPTXTargetMachine32::NVPTXTargetMachine32(

llvm/lib/Target/NVPTX/NVPTXTargetMachine.h

@@ -36,6 +36,8 @@ public:
                      const TargetOptions &Options, Reloc::Model RM,
                      CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit);
 
+  ~NVPTXTargetMachine() override;
+
   const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   ManagedStringPool *getManagedStrPool() const {

llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

@@ -85,6 +85,8 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
   initAsmInfo();
 }
 
+PPCTargetMachine::~PPCTargetMachine() {}
+
 void PPC32TargetMachine::anchor() { }
 
 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,

llvm/lib/Target/PowerPC/PPCTargetMachine.h

@@ -35,6 +35,8 @@ public:
                    Reloc::Model RM, CodeModel::Model CM,
                    CodeGenOpt::Level OL);
 
+  ~PPCTargetMachine() override;
+
   const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
   const PPCSubtarget *getSubtargetImpl(const Function &F) const override;
 

llvm/lib/Target/Sparc/SparcTargetMachine.cpp

@@ -38,6 +38,8 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
   initAsmInfo();
 }
 
+SparcTargetMachine::~SparcTargetMachine() {}
+
 namespace {
 /// Sparc Code Generator Pass Configuration Options.
 class SparcPassConfig : public TargetPassConfig {

llvm/lib/Target/Sparc/SparcTargetMachine.h

@@ -28,6 +28,7 @@ public:
                      StringRef CPU, StringRef FS, const TargetOptions &Options,
                      Reloc::Model RM, CodeModel::Model CM,
                      CodeGenOpt::Level OL, bool is64bit);
+  ~SparcTargetMachine() override;
 
   const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 

llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp

@@ -31,6 +31,8 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT,
   initAsmInfo();
 }
 
+SystemZTargetMachine::~SystemZTargetMachine() {}
+
 namespace {
 /// SystemZ Code Generator Pass Configuration Options.
 class SystemZPassConfig : public TargetPassConfig {

llvm/lib/Target/SystemZ/SystemZTargetMachine.h

@@ -31,6 +31,7 @@ public:
                        StringRef FS, const TargetOptions &Options,
                        Reloc::Model RM, CodeModel::Model CM,
                        CodeGenOpt::Level OL);
+  ~SystemZTargetMachine() override;
 
   // Override TargetMachine.
   const SystemZSubtarget *getSubtargetImpl() const override {

llvm/lib/Target/X86/X86TargetMachine.cpp

@@ -29,8 +29,6 @@ extern "C" void LLVMInitializeX86Target() {
   RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
 }
 
-void X86TargetMachine::anchor() { }
-
 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
   if (TT.isOSBinFormatMachO()) {
     if (TT.getArch() == Triple::x86_64)
@@ -72,6 +70,8 @@ X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
   initAsmInfo();
 }
 
+X86TargetMachine::~X86TargetMachine() {}
+
 const X86Subtarget *
 X86TargetMachine::getSubtargetImpl(const Function &F) const {
   AttributeSet FnAttrs = F.getAttributes();

llvm/lib/Target/X86/X86TargetMachine.h

@@ -23,7 +23,6 @@ namespace llvm {
 class StringRef;
 
 class X86TargetMachine final : public LLVMTargetMachine {
-  virtual void anchor();
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   X86Subtarget       Subtarget;
 
@@ -34,6 +33,8 @@ public:
                    StringRef CPU, StringRef FS, const TargetOptions &Options,
                    Reloc::Model RM, CodeModel::Model CM,
                    CodeGenOpt::Level OL);
+  ~X86TargetMachine() override;
+
   const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
   const X86Subtarget *getSubtargetImpl(const Function &F) const override;
 

llvm/lib/Target/XCore/XCoreTargetMachine.cpp

@@ -32,6 +32,8 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
   initAsmInfo();
 }
 
+XCoreTargetMachine::~XCoreTargetMachine() {}
+
 namespace {
 /// XCore Code Generator Pass Configuration Options.
 class XCorePassConfig : public TargetPassConfig {

llvm/lib/Target/XCore/XCoreTargetMachine.h

@@ -27,6 +27,7 @@ public:
                      StringRef CPU, StringRef FS, const TargetOptions &Options,
                      Reloc::Model RM, CodeModel::Model CM,
                      CodeGenOpt::Level OL);
+  ~XCoreTargetMachine() override;
 
   const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; }