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[AArch64] Handle ISD::LRINT and ISD::LLRINT 

This patch optimizes ISD::LRINT and ISD::LLRINT to frintx plus
fcvtzs. It currently only handles the scalar version.

Reviewed By: SjoerdMeijer, mstorsjo

Differential Revision: https://reviews.llvm.org/D62018

llvm-svn: 361877
This commit is contained in:
Adhemerval Zanella 2019-05-28 21:04:29 +00:00
parent ccc1fa5e1d
commit 34d8daae53
6 changed files with 89 additions and 8 deletions
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2
llvm/include/llvm/Target/TargetSelectionDAG.td
View File

@ -453,6 +453,8 @@ def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
def lround : SDNode<"ISD::LROUND" , SDTFPToIntOp>;
def llround : SDNode<"ISD::LLROUND" , SDTFPToIntOp>;
def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>;
def llrint : SDNode<"ISD::LLRINT" , SDTFPToIntOp>;
def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;

2
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -459,6 +459,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FMAXIMUM, Ty, Legal);
setOperationAction(ISD::LROUND, Ty, Legal);
setOperationAction(ISD::LLROUND, Ty, Legal);
setOperationAction(ISD::LRINT, Ty, Legal);
setOperationAction(ISD::LLRINT, Ty, Legal);
}
if (Subtarget->hasFullFP16()) {

13
llvm/lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -3160,6 +3160,19 @@ let Predicates = [HasFRInt3264] in {
defm FRINT64X : FRIntNNT<0b11, "frint64x">;
} // HasFRInt3264
def : Pat<(i32 (lrint f32:$Rn)),
(FCVTZSUWSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
def : Pat<(i32 (lrint f64:$Rn)),
(FCVTZSUWDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
def : Pat<(i64 (lrint f32:$Rn)),
(FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
def : Pat<(i64 (lrint f64:$Rn)),
(FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
def : Pat<(i64 (llrint f32:$Rn)),
(FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
def : Pat<(i64 (llrint f64:$Rn)),
(FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
//===----------------------------------------------------------------------===//
// Floating point two operand instructions.
//===----------------------------------------------------------------------===//

16
llvm/test/CodeGen/AArch64/llrint-conv.ll
View File

@ -1,7 +1,9 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
; CHECK-LABEL: testmsws:
; CHECK: bl llrintf
; CHECK: frintx [[REG:s[0-9]]], s0
; CHECK-NEXT: fcvtzs x0, [[REG]]
; CHECK: ret
define i32 @testmsws(float %x) {
entry:
%0 = tail call i64 @llvm.llrint.f32(float %x)
@ -10,7 +12,9 @@ entry:
}
; CHECK-LABEL: testmsxs:
; CHECK: b llrintf
; CHECK: frintx [[REG:s[0-9]]], s0
; CHECK-NEXT: fcvtzs x0, [[REG]]
; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i64 @llvm.llrint.f32(float %x)
@ -18,7 +22,9 @@ entry:
}
; CHECK-LABEL: testmswd:
; CHECK: bl llrint
; CHECK: frintx [[REG:d[0-9]]], d0
; CHECK-NEXT: fcvtzs x0, [[REG]]
; CHECK: ret
define i32 @testmswd(double %x) {
entry:
%0 = tail call i64 @llvm.llrint.f64(double %x)
@ -27,7 +33,9 @@ entry:
}
; CHECK-LABEL: testmsxd:
; CHECK: b llrint
; CHECK: frintx [[REG:d[0-9]]], d0
; CHECK-NEXT: fcvtzs x0, [[REG]]
; CHECK-nEXT: ret
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i64 @llvm.llrint.f64(double %x)

48
llvm/test/CodeGen/AArch64/lrint-conv-win.ll Normal file
View File

@ -0,0 +1,48 @@
; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
; CHECK-LABEL: testmsxs:
; CHECK: frintx [[SREG:s[0-9]+]], s0
; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]]
; CHECK-NEXT: sxtw x0, [[WREG]]
; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f32(float %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
; CHECK-LABEL: testmsws:
; CHECK: frintx [[SREG:s[0-9]+]], s0
; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]]
; CHECK-NEXT: ret
define i32 @testmsws(float %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f32(float %x)
ret i32 %0
}
; CHECK-LABEL: testmsxd:
; CHECK: frintx [[DREG:d[0-9]+]], d0
; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]]
; CHECK-NEXT: sxtw x0, [[WREG]]
; CHECK-NEXT: ret
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f64(double %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
; CHECK-LABEL: testmswd:
; CHECK: frintx [[DREG:d[0-9]+]], d0
; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]]
; CHECK-NEXT: ret
define i32 @testmswd(double %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f64(double %x)
ret i32 %0
}
declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
declare i32 @llvm.lrint.i32.f64(double) nounwind readnone

16
llvm/test/CodeGen/AArch64/lrint-conv.ll
View File

@ -1,7 +1,9 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
; CHECK-LABEL: testmsws:
; CHECK: bl lrintf
; CHECK: frintx [[REG:s[0-9]]], s0
; CHECK-NEXT: fcvtzs x0, [[REG]]
; CHECK: ret
define i32 @testmsws(float %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f32(float %x)
@ -10,7 +12,9 @@ entry:
}
; CHECK-LABEL: testmsxs:
; CHECK: b lrintf
; CHECK: frintx [[REG:s[0-9]]], s0
; CHECK-NEXT: fcvtzs x0, [[REG]]
; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f32(float %x)
@ -18,7 +22,9 @@ entry:
}
; CHECK-LABEL: testmswd:
; CHECK: bl lrint
; CHECK: frintx [[REG:d[0-9]]], d0
; CHECK-NEXT: fcvtzs x0, [[REG]]
; CHECK: ret
define i32 @testmswd(double %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f64(double %x)
@ -27,7 +33,9 @@ entry:
}
; CHECK-LABEL: testmsxd:
; CHECK: b lrint
; CHECK: frintx [[REG:d[0-9]]], d0
; CHECK-NEXT: fcvtzs x0, [[REG]]
; CHECK-NEXT: ret
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f64(double %x)