Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
llvm-svn: 194086
This commit is contained in:
Jiangning Liu
parent
d7c52676f6
commit
34a7109b47
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@ -768,6 +768,25 @@ def VADDV : SInst<"vaddv", "sd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def FMAXNMV : SInst<"vmaxnmv", "sd", "Qf">;
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def FMINNMV : SInst<"vminnmv", "sd", "Qf">;
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////////////////////////////////////////////////////////////////////////////////
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// Crypto
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def AESE : SInst<"vaese", "ddd", "QUc">;
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def AESD : SInst<"vaesd", "ddd", "QUc">;
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def AESMC : SInst<"vaesmc", "dd", "QUc">;
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def AESIMC : SInst<"vaesimc", "dd", "QUc">;
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def SHA1H : SInst<"vsha1h", "ss", "Ui">;
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def SHA1SU1 : SInst<"vsha1su1", "ddd", "QUi">;
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def SHA256SU0 : SInst<"vsha256su0", "ddd", "QUi">;
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def SHA1C : SInst<"vsha1c", "ddsd", "QUi">;
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def SHA1P : SInst<"vsha1p", "ddsd", "QUi">;
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def SHA1M : SInst<"vsha1m", "ddsd", "QUi">;
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def SHA1SU0 : SInst<"vsha1su0", "dddd", "QUi">;
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def SHA256H : SInst<"vsha256h", "dddd", "QUi">;
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def SHA256H2 : SInst<"vsha256h2", "dddd", "QUi">;
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def SHA256SU1 : SInst<"vsha256su1", "dddd", "QUi">;
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////////////////////////////////////////////////////////////////////////////////
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// Scalar Arithmetic
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@ -1770,6 +1770,45 @@ static Value *EmitAArch64ScalarBuiltinExpr(CodeGenFunction &CGF,
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// argument that specifies the vector type, need to handle each case.
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switch (BuiltinID) {
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default: break;
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case AArch64::BI__builtin_neon_vget_lane_i8:
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case AArch64::BI__builtin_neon_vget_lane_i16:
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case AArch64::BI__builtin_neon_vget_lane_i32:
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case AArch64::BI__builtin_neon_vget_lane_i64:
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case AArch64::BI__builtin_neon_vget_lane_f32:
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case AArch64::BI__builtin_neon_vget_lane_f64:
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case AArch64::BI__builtin_neon_vgetq_lane_i8:
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case AArch64::BI__builtin_neon_vgetq_lane_i16:
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case AArch64::BI__builtin_neon_vgetq_lane_i32:
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case AArch64::BI__builtin_neon_vgetq_lane_i64:
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case AArch64::BI__builtin_neon_vgetq_lane_f32:
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case AArch64::BI__builtin_neon_vgetq_lane_f64:
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return CGF.EmitARMBuiltinExpr(ARM::BI__builtin_neon_vget_lane_i8, E);
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case AArch64::BI__builtin_neon_vset_lane_i8:
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case AArch64::BI__builtin_neon_vset_lane_i16:
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case AArch64::BI__builtin_neon_vset_lane_i32:
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case AArch64::BI__builtin_neon_vset_lane_i64:
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case AArch64::BI__builtin_neon_vset_lane_f32:
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case AArch64::BI__builtin_neon_vset_lane_f64:
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case AArch64::BI__builtin_neon_vsetq_lane_i8:
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case AArch64::BI__builtin_neon_vsetq_lane_i16:
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case AArch64::BI__builtin_neon_vsetq_lane_i32:
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case AArch64::BI__builtin_neon_vsetq_lane_i64:
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case AArch64::BI__builtin_neon_vsetq_lane_f32:
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case AArch64::BI__builtin_neon_vsetq_lane_f64:
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return CGF.EmitARMBuiltinExpr(ARM::BI__builtin_neon_vset_lane_i8, E);
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// Crypto
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case AArch64::BI__builtin_neon_vsha1h_u32:
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Int = Intrinsic::arm_neon_sha1h;
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s = "sha1h"; OverloadInt = true; break;
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case AArch64::BI__builtin_neon_vsha1cq_u32:
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Int = Intrinsic::aarch64_neon_sha1c;
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s = "sha1c"; break;
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case AArch64::BI__builtin_neon_vsha1pq_u32:
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Int = Intrinsic::aarch64_neon_sha1p;
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s = "sha1p"; break;
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case AArch64::BI__builtin_neon_vsha1mq_u32:
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Int = Intrinsic::aarch64_neon_sha1m;
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s = "sha1m"; break;
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// Scalar Add
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case AArch64::BI__builtin_neon_vaddd_s64:
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Int = Intrinsic::aarch64_neon_vaddds;
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@ -2434,36 +2473,6 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
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for (unsigned i = 0, e = E->getNumArgs() - 1; i != e; i++) {
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Ops.push_back(EmitScalarExpr(E->getArg(i)));
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}
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// Some intrinsic isn't overloaded.
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switch (BuiltinID) {
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default: break;
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case AArch64::BI__builtin_neon_vget_lane_i8:
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case AArch64::BI__builtin_neon_vget_lane_i16:
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case AArch64::BI__builtin_neon_vget_lane_i32:
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case AArch64::BI__builtin_neon_vget_lane_i64:
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case AArch64::BI__builtin_neon_vget_lane_f32:
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case AArch64::BI__builtin_neon_vget_lane_f64:
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case AArch64::BI__builtin_neon_vgetq_lane_i8:
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case AArch64::BI__builtin_neon_vgetq_lane_i16:
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case AArch64::BI__builtin_neon_vgetq_lane_i32:
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case AArch64::BI__builtin_neon_vgetq_lane_i64:
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case AArch64::BI__builtin_neon_vgetq_lane_f32:
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case AArch64::BI__builtin_neon_vgetq_lane_f64:
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return EmitARMBuiltinExpr(ARM::BI__builtin_neon_vget_lane_i8, E);
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case AArch64::BI__builtin_neon_vset_lane_i8:
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case AArch64::BI__builtin_neon_vset_lane_i16:
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case AArch64::BI__builtin_neon_vset_lane_i32:
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case AArch64::BI__builtin_neon_vset_lane_i64:
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case AArch64::BI__builtin_neon_vset_lane_f32:
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case AArch64::BI__builtin_neon_vset_lane_f64:
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case AArch64::BI__builtin_neon_vsetq_lane_i8:
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case AArch64::BI__builtin_neon_vsetq_lane_i16:
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case AArch64::BI__builtin_neon_vsetq_lane_i32:
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case AArch64::BI__builtin_neon_vsetq_lane_i64:
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case AArch64::BI__builtin_neon_vsetq_lane_f32:
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case AArch64::BI__builtin_neon_vsetq_lane_f64:
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return EmitARMBuiltinExpr(ARM::BI__builtin_neon_vset_lane_i8, E);
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}
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// Get the last argument, which specifies the vector type.
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llvm::APSInt Result;
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@ -2769,6 +2778,38 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
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case AArch64::BI__builtin_neon_vst4q_v:
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return EmitARMBuiltinExpr(ARM::BI__builtin_neon_vst4q_v, E);
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// Crypto
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case AArch64::BI__builtin_neon_vaeseq_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_aese, Ty),
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Ops, "aese");
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case AArch64::BI__builtin_neon_vaesdq_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_aesd, Ty),
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Ops, "aesd");
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case AArch64::BI__builtin_neon_vaesmcq_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_aesmc, Ty),
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Ops, "aesmc");
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case AArch64::BI__builtin_neon_vaesimcq_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_aesimc, Ty),
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Ops, "aesimc");
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case AArch64::BI__builtin_neon_vsha1su1q_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_sha1su1, Ty),
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Ops, "sha1su1");
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case AArch64::BI__builtin_neon_vsha256su0q_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_sha256su0, Ty),
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Ops, "sha256su0");
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case AArch64::BI__builtin_neon_vsha1su0q_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_sha1su0, Ty),
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Ops, "sha1su0");
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case AArch64::BI__builtin_neon_vsha256hq_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_sha256h, Ty),
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Ops, "sha256h");
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case AArch64::BI__builtin_neon_vsha256h2q_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_sha256h2, Ty),
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Ops, "sha256h2");
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case AArch64::BI__builtin_neon_vsha256su1q_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_sha256su1, Ty),
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Ops, "sha256su1");
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// AArch64-only builtins
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case AArch64::BI__builtin_neon_vfma_lane_v:
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case AArch64::BI__builtin_neon_vfmaq_laneq_v: {
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@ -0,0 +1,91 @@
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// REQUIRES: aarch64-registered-target
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
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// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
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// Test new aarch64 intrinsics and types
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#include <arm_neon.h>
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uint8x16_t test_vaeseq_u8(uint8x16_t data, uint8x16_t key) {
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// CHECK: test_vaeseq_u8
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return vaeseq_u8(data, key);
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// CHECK: aese {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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}
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uint8x16_t test_vaesdq_u8(uint8x16_t data, uint8x16_t key) {
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// CHECK: test_vaesdq_u8
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return vaesdq_u8(data, key);
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// CHECK: aesd {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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}
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uint8x16_t test_vaesmcq_u8(uint8x16_t data) {
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// CHECK: test_vaesmcq_u8
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return vaesmcq_u8(data);
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// CHECK: aesmc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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}
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uint8x16_t test_vaesimcq_u8(uint8x16_t data) {
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// CHECK: test_vaesimcq_u8
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return vaesimcq_u8(data);
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// CHECK: aesimc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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}
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uint32_t test_vsha1h_u32(uint32_t hash_e) {
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// CHECK: test_vsha1h_u32
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return vsha1h_u32(hash_e);
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// CHECK: sha1h {{s[0-9]+}}, {{s[0-9]+}}
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}
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uint32x4_t test_vsha1su1q_u32(uint32x4_t tw0_3, uint32x4_t w12_15) {
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// CHECK: test_vsha1su1q_u32
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return vsha1su1q_u32(tw0_3, w12_15);
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// CHECK: sha1su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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}
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uint32x4_t test_vsha256su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7) {
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// CHECK: test_vsha256su0q_u32
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return vsha256su0q_u32(w0_3, w4_7);
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// CHECK: sha256su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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}
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uint32x4_t test_vsha1cq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) {
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// CHECK: test_vsha1cq_u32
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return vsha1cq_u32(hash_abcd, hash_e, wk);
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// CHECK: sha1c {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
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}
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uint32x4_t test_vsha1pq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) {
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// CHECK: test_vsha1pq_u32
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return vsha1pq_u32(hash_abcd, hash_e, wk);
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// CHECK: sha1p {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
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}
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uint32x4_t test_vsha1mq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) {
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// CHECK: test_vsha1mq_u32
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return vsha1mq_u32(hash_abcd, hash_e, wk);
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// CHECK: sha1m {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
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}
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uint32x4_t test_vsha1su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11) {
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// CHECK: test_vsha1su0q_u32
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return vsha1su0q_u32(w0_3, w4_7, w8_11);
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// CHECK: sha1su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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}
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uint32x4_t test_vsha256hq_u32(uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk) {
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// CHECK: test_vsha256hq_u32
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return vsha256hq_u32(hash_abcd, hash_efgh, wk);
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// CHECK: sha256h {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s
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}
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uint32x4_t test_vsha256h2q_u32(uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk) {
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// CHECK: test_vsha256h2q_u32
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return vsha256h2q_u32(hash_efgh, hash_abcd, wk);
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// CHECK: sha256h2 {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s
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}
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uint32x4_t test_vsha256su1q_u32(uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15) {
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// CHECK: test_vsha256su1q_u32
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return vsha256su1q_u32(tw0_3, w8_11, w12_15);
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// CHECK: sha256su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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}
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