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[AMDGPU] Fix incorrect register pressure calculation 

Earlier fix D32572 introduced a bug where live-ins were calculated
for basic block instead of scheduling region. This change fixes it.

Differential Revision: https://reviews.llvm.org/D33086

llvm-svn: 302812
This commit is contained in:
Stanislav Mekhanoshin 2017-05-11 17:16:55 +00:00
parent 0aca09fc6c
commit 33a97ec4ed
1 changed files with 3 additions and 2 deletions
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5
llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
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@ -422,9 +422,10 @@ void GCNScheduleDAGMILive::discoverLiveIns() {
unsigned SGPRs = 0;
unsigned VGPRs = 0;
auto &MI = *begin()->getParent()->getFirstNonDebugInstr();
auto I = begin();
I = skipDebugInstructionsForward(I, I->getParent()->end());
const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI);
SlotIndex SI = LIS->getInstructionIndex(MI).getBaseIndex();
SlotIndex SI = LIS->getInstructionIndex(*I).getBaseIndex();
assert (SI.isValid());
DEBUG(dbgs() << "Region live-ins:");