[mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary: RET, and RET_MM have been replaced by a pseudo named PseudoReturn. In addition a version with a 64-bit GPR named PseudoReturn64 has been added. Instruction selection for a return matches RetRA, which is expanded post register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter, this PseudoReturn/PseudoReturn64 are emitted as: - (JALR64 $zero, $rs) on MIPS64r6 - (JALR $zero, $rs) on MIPS32r6 - (JR_MM $rs) on microMIPS - (JR $rs) otherwise On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid development and review (specifically, to ensure all cases of jr are updated), these aliases are temporarily named 'r6.jr' instead of 'jr'. A follow up patch will change them back to the correct mnemonic. Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect jump, and removed it from its definition of a call. Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's doesn't appear to account for any MIPS64-specifics. The return instruction created as part of eh_return expansion is now expanded using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6 ('jalr $zero, $rs'). Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in expandEhReturn(). Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4268 llvm-svn: 212604
This commit is contained in:
parent
123c38de3b
commit
338513b3fa
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@ -48,7 +48,13 @@ private:
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bool PendingCall;
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bool isIndirectJump(const MCInst &MI) {
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return MI.getOpcode() == Mips::JR || MI.getOpcode() == Mips::RET;
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if (MI.getOpcode() == Mips::JALR) {
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// MIPS32r6/MIPS64r6 doesn't have a JR instruction and uses JALR instead.
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// JALR is an indirect branch if the link register is $0.
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assert(MI.getOperand(0).isReg());
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return MI.getOperand(0).getReg() == Mips::ZERO;
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}
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return MI.getOpcode() == Mips::JR;
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}
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bool isStackPointerFirstOperand(const MCInst &MI) {
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@ -56,7 +62,9 @@ private:
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&& MI.getOperand(0).getReg() == Mips::SP);
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}
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bool isCall(unsigned Opcode, bool *IsIndirectCall) {
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bool isCall(const MCInst &MI, bool *IsIndirectCall) {
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unsigned Opcode = MI.getOpcode();
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*IsIndirectCall = false;
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switch (Opcode) {
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@ -71,6 +79,12 @@ private:
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return true;
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case Mips::JALR:
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// JALR is only a call if the link register is not $0. Otherwise it's an
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// indirect branch.
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assert(MI.getOperand(0).isReg());
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if (MI.getOperand(0).getReg() == Mips::ZERO)
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return false;
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*IsIndirectCall = true;
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return true;
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}
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@ -154,7 +168,7 @@ public:
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// Sandbox calls by aligning call and branch delay to the bundle end.
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// For indirect calls, emit the mask before the call.
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bool IsIndirectCall;
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if (isCall(Inst.getOpcode(), &IsIndirectCall)) {
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if (isCall(Inst, &IsIndirectCall)) {
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if (PendingCall)
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report_fatal_error("Dangerous instruction in branch delay slot!");
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@ -246,7 +246,6 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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}
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def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
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def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
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def RET_MM : MMRel, RetBase<"ret", GPR32Opnd>, JR_FM_MM<0x3c>;
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/// Branch Instructions
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def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
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@ -733,6 +733,7 @@ def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
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//===----------------------------------------------------------------------===//
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def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
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def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6;
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//===----------------------------------------------------------------------===//
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//
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@ -186,6 +186,8 @@ def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
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def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
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}
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def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
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/// Multiply and Divide Instructions.
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def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
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@ -105,6 +105,14 @@ let DecoderNamespace = "Mips32r6_64r6_GP64" in {
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def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Aliases
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//
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//===----------------------------------------------------------------------===//
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def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
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//===----------------------------------------------------------------------===//
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//
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// Patterns and Pseudo Instructions
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@ -91,6 +91,42 @@ bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
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#include "MipsGenMCPseudoLowering.inc"
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void MipsAsmPrinter::emitPseudoReturn(MCStreamer &OutStreamer,
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const MachineInstr *MI) {
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// Lower PseudoReturn to JR, JR_MM, JALR, or JALR64 as appropriate for the
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// target
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bool HasLinkReg = false;
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MCInst TmpInst0;
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if (Subtarget->hasMips64r6()) {
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// MIPS64r6 should use (JALR64 ZERO_64, $rs)
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TmpInst0.setOpcode(Mips::JALR64);
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HasLinkReg = true;
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} else if (Subtarget->hasMips32r6()) {
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// MIPS32r6 should use (JALR ZERO, $rs)
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TmpInst0.setOpcode(Mips::JALR);
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HasLinkReg = true;
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} else if (Subtarget->inMicroMipsMode())
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// microMIPS should use (JR_MM $rs)
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TmpInst0.setOpcode(Mips::JR_MM);
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else {
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// Everything else should use (JR $rs)
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TmpInst0.setOpcode(Mips::JR);
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}
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MCOperand MCOp;
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if (HasLinkReg) {
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unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
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TmpInst0.addOperand(MCOperand::CreateReg(ZeroReg));
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}
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lowerOperand(MI->getOperand(0), MCOp);
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TmpInst0.addOperand(MCOp);
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EmitToStreamer(OutStreamer, TmpInst0);
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}
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void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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MipsTargetStreamer &TS = getTargetStreamer();
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TS.setCanHaveModuleDir(false);
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@ -144,6 +180,12 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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if (emitPseudoExpansionLowering(OutStreamer, &*I))
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continue;
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if (I->getOpcode() == Mips::PseudoReturn ||
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I->getOpcode() == Mips::PseudoReturn64) {
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emitPseudoReturn(OutStreamer, &*I);
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continue;
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}
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// The inMips16Mode() test is not permanent.
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// Some instructions are marked as pseudo right now which
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// would make the test fail for the wrong reason but
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@ -40,6 +40,8 @@ private:
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bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
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const MachineInstr *MI);
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void emitPseudoReturn(MCStreamer &OutStreamer, const MachineInstr *MI);
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// lowerOperand - Convert a MachineOperand into the equivalent MCOperand.
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bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp);
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@ -749,14 +749,6 @@ class IndirectBranch<string opstr, RegisterOperand RO> :
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let isIndirectBranch = 1;
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}
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// Return instruction
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class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
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let isReturn = 1;
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let isCodeGenOnly = 1;
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let hasCtrlDep = 1;
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let hasExtraSrcRegAllocReq = 1;
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}
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1, Defs = [RA] in {
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class JumpLink<string opstr, DAGOperand opnd> :
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def TAILCALL : TailCall<J>;
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def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
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def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
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// Return instruction
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// RetRA is expanded into this after register allocation and then MipsAsmPrinter
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// expands this into JR, or JALR depending on the ISA.
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class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
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[], IIBranch> {
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let isTerminator = 1;
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let isBarrier = 1;
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let hasDelaySlot = 1;
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let isReturn = 1;
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let isCodeGenOnly = 1;
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let hasCtrlDep = 1;
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let hasExtraSrcRegAllocReq = 1;
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}
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def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
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// Exception handling related node and instructions.
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// The conversion sequence is:
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@ -272,7 +272,7 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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default:
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return false;
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case Mips::RetRA:
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expandRetRA(MBB, MI, Mips::RET);
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expandRetRA(MBB, MI);
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break;
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case Mips::PseudoMFHI:
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Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
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}
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void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Opc) const {
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BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
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MachineBasicBlock::iterator I) const {
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const auto &Subtarget = TM.getSubtarget<MipsSubtarget>();
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if (Subtarget.isGP64bit())
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BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
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.addReg(Mips::RA_64);
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else
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BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA);
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}
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std::pair<bool, bool>
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// indirect jump to TargetReg
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const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
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unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
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unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
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unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned SP = STI.isGP64bit() ? Mips::SP_64 : Mips::SP;
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unsigned RA = STI.isGP64bit() ? Mips::RA_64 : Mips::RA;
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unsigned T9 = STI.isGP64bit() ? Mips::T9_64 : Mips::T9;
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unsigned ZERO = STI.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned OffsetReg = I->getOperand(0).getReg();
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unsigned TargetReg = I->getOperand(1).getReg();
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// addu $ra, $v0, $zero
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// addu $sp, $sp, $v1
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// jr $ra
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// jr $ra (via RetRA)
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if (TM.getRelocationModel() == Reloc::PIC_)
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BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
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.addReg(TargetReg).addReg(ZERO);
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.addReg(TargetReg).addReg(ZERO);
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BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
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.addReg(SP).addReg(OffsetReg);
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BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
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expandRetRA(MBB, I);
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}
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const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
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private:
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unsigned getAnalyzableBrOpc(unsigned Opc) const override;
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void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned Opc) const;
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void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
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std::pair<bool, bool> compareOpndSize(unsigned Opc,
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const MachineFunction &MF) const;
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@ -1,4 +1,6 @@
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; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
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; RUN: llc -march=mipsel -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
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; RUN: llc -march=mipsel -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=R6
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declare void @llvm.eh.return.i32(i32, i8*)
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declare void @foo(...)
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call void @llvm.eh.return.i32(i32 %offset, i8* %handler)
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unreachable
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; CHECK: f1
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; CHECK: f1:
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; CHECK: addiu $sp, $sp, -[[spoffset:[0-9]+]]
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; check that $a0-$a3 are saved on stack.
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; CHECK: addiu $sp, $sp, [[spoffset]]
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; CHECK: move $25, $2
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; CHECK: move $ra, $2
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; CHECK: jr $ra
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; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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; CHECK: addu $sp, $sp, $3
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}
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call void @llvm.eh.return.i32(i32 %offset, i8* %handler)
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unreachable
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; CHECK: f2
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; CHECK: f2:
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; CHECK: addiu $sp, $sp, -[[spoffset:[0-9]+]]
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; check that $a0-$a3 are saved on stack.
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; CHECK: addiu $sp, $sp, [[spoffset]]
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; CHECK: move $25, $2
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; CHECK: move $ra, $2
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; CHECK: jr $ra
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; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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; CHECK: addu $sp, $sp, $3
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}
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@ -1,5 +1,7 @@
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; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
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; RUN: llc -march=mips64el -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
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; RUN: llc -march=mips64el -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
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; RUN: llc -march=mips64el -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
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; RUN: llc -march=mips64el -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=R6
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declare void @llvm.eh.return.i64(i64, i8*)
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declare void @foo(...)
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call void @llvm.eh.return.i64(i64 %offset, i8* %handler)
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unreachable
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; CHECK: f1
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; CHECK: f1:
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; CHECK: daddiu $sp, $sp, -[[spoffset:[0-9]+]]
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; check that $a0-$a3 are saved on stack.
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@ -42,9 +44,9 @@ entry:
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; CHECK: daddiu $sp, $sp, [[spoffset]]
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; CHECK: move $25, $2
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; CHECK: move $ra, $2
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; CHECK: jr $ra
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; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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; CHECK: daddu $sp, $sp, $3
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}
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define void @f2(i64 %offset, i8* %handler) {
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call void @llvm.eh.return.i64(i64 %offset, i8* %handler)
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unreachable
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; CHECK: f2
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; CHECK: f2:
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; CHECK: .cfi_startproc
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; CHECK: daddiu $sp, $sp, -[[spoffset:[0-9]+]]
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; CHECK: .cfi_def_cfa_offset [[spoffset]]
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@ -84,7 +86,8 @@ entry:
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; CHECK: daddiu $sp, $sp, [[spoffset]]
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; CHECK: move $25, $2
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; CHECK: move $ra, $2
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; CHECK: jr $ra
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; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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; CHECK: daddu $sp, $sp, $3
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; CHECK: .cfi_endproc
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}
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|
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@ -4,67 +4,94 @@
|
|||
; test constant generation here.
|
||||
;
|
||||
; We'll test pointer returns in a separate file since the relocation model
|
||||
; affects it.
|
||||
; affects it and it's undesirable to repeat the non-pointer returns for each
|
||||
; relocation model.
|
||||
|
||||
; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1
|
||||
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1
|
||||
; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1
|
||||
; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1
|
||||
; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6
|
||||
|
||||
define void @ret_void() {
|
||||
; ALL-LABEL: ret_void:
|
||||
; ALL: jr $ra
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define i8 @ret_i8() {
|
||||
; ALL-LABEL: ret_i8:
|
||||
; ALL-DAG: jr $ra
|
||||
; ALL-DAG: addiu $2, $zero, 3
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i8 3
|
||||
}
|
||||
|
||||
define i16 @ret_i16_3() {
|
||||
; ALL-LABEL: ret_i16_3:
|
||||
; ALL-DAG: jr $ra
|
||||
; ALL-DAG: addiu $2, $zero, 3
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i16 3
|
||||
}
|
||||
|
||||
define i16 @ret_i16_256() {
|
||||
; ALL-LABEL: ret_i16_256:
|
||||
; ALL-DAG: jr $ra
|
||||
; ALL-DAG: addiu $2, $zero, 256
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i16 256
|
||||
}
|
||||
|
||||
define i16 @ret_i16_257() {
|
||||
; ALL-LABEL: ret_i16_257:
|
||||
; ALL-DAG: jr $ra
|
||||
; ALL-DAG: addiu $2, $zero, 257
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i16 257
|
||||
}
|
||||
|
||||
define i32 @ret_i32_257() {
|
||||
; ALL-LABEL: ret_i32_257:
|
||||
; ALL-DAG: jr $ra
|
||||
; ALL-DAG: addiu $2, $zero, 257
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i32 257
|
||||
}
|
||||
|
||||
define i32 @ret_i32_65536() {
|
||||
; ALL-LABEL: ret_i32_65536:
|
||||
; ALL-DAG: jr $ra
|
||||
; ALL-DAG: lui $2, 1
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i32 65536
|
||||
}
|
||||
|
||||
define i32 @ret_i32_65537() {
|
||||
; ALL-LABEL: ret_i32_65537:
|
||||
; ALL: lui $[[T0:[0-9]+]], 1
|
||||
; ALL-DAG: jr $ra
|
||||
; ALL-DAG: ori $2, $[[T0]], 1
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i32 65537
|
||||
}
|
||||
|
||||
|
@ -77,7 +104,9 @@ define i64 @ret_i64_65537() {
|
|||
|
||||
; GPR64-DAG: daddiu $2, $[[T0]], 1
|
||||
|
||||
; ALL-DAG: jr $ra
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i64 65537
|
||||
}
|
||||
|
||||
|
@ -91,7 +120,9 @@ define i64 @ret_i64_281479271677952() {
|
|||
; GPR64-DAG: daddiu $[[T1:[0-9]+]], $[[T0]], 1
|
||||
; GPR64-DAG: dsll $2, $[[T1]], 32
|
||||
|
||||
; ALL-DAG: jr $ra
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i64 281479271677952
|
||||
}
|
||||
|
||||
|
@ -108,11 +139,12 @@ define i64 @ret_i64_281479271809026() {
|
|||
; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 17
|
||||
; GPR64-DAG: daddiu $2, $[[T1]], 2
|
||||
|
||||
; ALL-DAG: jr $ra
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret i64 281479271809026
|
||||
}
|
||||
|
||||
; TODO: f32
|
||||
define float @ret_float_0x0() {
|
||||
; ALL-LABEL: ret_float_0x0:
|
||||
|
||||
|
@ -122,7 +154,9 @@ define float @ret_float_0x0() {
|
|||
|
||||
; DMTC-DAG: dmtc1 $zero, $f0
|
||||
|
||||
; ALL-DAG: jr $ra
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret float 0x0000000000000000
|
||||
}
|
||||
|
||||
|
@ -133,7 +167,8 @@ define float @ret_float_0x3() {
|
|||
; O32-DAG: lwc1 $f0, %lo($CPI
|
||||
; N64-DAG: lwc1 $f0, %got_ofst($CPI
|
||||
|
||||
; ALL-DAG: jr $ra
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
; float constants are written as double constants
|
||||
ret float 0x36b8000000000000
|
||||
|
@ -150,7 +185,9 @@ define double @ret_double_0x0() {
|
|||
|
||||
; DMTC-DAG: dmtc1 $zero, $f0
|
||||
|
||||
; ALL-DAG: jr $ra
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret double 0x0000000000000000
|
||||
}
|
||||
|
||||
|
@ -161,6 +198,8 @@ define double @ret_double_0x3() {
|
|||
; O32-DAG: ldc1 $f0, %lo($CPI
|
||||
; N64-DAG: ldc1 $f0, %got_ofst($CPI
|
||||
|
||||
; ALL-DAG: jr $ra
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
|
||||
ret double 0x0000000000000003
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue