replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[Hexagon] Avoid predicate copies to integer registers from store-locked 

llvm-svn: 332260
This commit is contained in:
Krzysztof Parzyszek 2018-05-14 16:41:40 +00:00
parent 6b8b868db5
commit 329c3e9a5f
4 changed files with 22 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
llvm/lib/Target/Hexagon/HexagonPatterns.td
View File

@ -2910,3 +2910,18 @@ def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf,
[SDNPHasChain]>;
def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>;
// The declared return value of the store-locked intrinsics is i32, but
// the instructions actually define i1. To avoid register copies from
// IntRegs to PredRegs and back, fold the entire pattern checking the
// result against true/false.
let AddedComplexity = 100 in {
def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)),
(S2_storew_locked I32:$Rs, I32:$Rt)>;
def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)),
(C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>;
def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)),
(S4_stored_locked I32:$Rs, I64:$Rt)>;
def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)),
(C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>;
}

6
llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll
View File

@ -39,7 +39,7 @@ BINARY_OP_entry:
; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memw(gp+#i32Result) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
@ -60,7 +60,7 @@ entry:
; CHECK: [[RESULT_REG:r[0-9]+:[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memd(gp+#i64Result) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
@ -81,7 +81,7 @@ entry:
; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memw(gp+#ptrResult) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31

4
llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll
View File

@ -32,7 +32,7 @@
; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memw(gp+#g2) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
define void @f0() {
@ -53,7 +53,7 @@ BINARY_OP_entry:
; CHECK: [[RESULT_REG:r[:0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memd(gp+#g5) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
define void @f1() {

4
llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll
View File

@ -22,7 +22,7 @@
; CHECK: [[RESULT_REG:r[0-9]+]] = sub(#-1,[[AND_RESULT_REG]])
; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memw(gp+#g2) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
define void @f0() {
@ -44,7 +44,7 @@ b0:
; CHECK: [[RESULT_REG:r[:0-9]+]] = not([[AND_RESULT_REG]])
; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
; CHECK-DAG: memd(gp+#g5) = [[LOCKED_READ_REG]]
; CHECK-DAG: jumpr r31
define void @f1() {