Fix ARM unwind opcode assembler in several cases.
Changes to ARM unwind opcode assembler:
* Fix multiple .save or .vsave directives. Besides, the
order is preserved now.
* For the directives which will generate multiple opcodes,
such as ".save {r0-r11}", the order of the unwind opcode
is fixed now, i.e. the registers with less encoding value
are popped first.
* Fix the $sp offset calculation. Now, we can use the
.setfp, .pad, .save, and .vsave directives at any order.
Changes to test cases:
* Add test cases to check the order of multiple opcodes
for the .save directive.
* Fix the incorrect $sp offset in the test case. The
stack pointer offset specified in the test case was
incorrect. (Changed test cases: ehabi-mc-section.ll and
ehabi-mc.ll)
* The opcode to restore $sp are slightly reordered. The
behavior are not changed, and the new output is same
as the output of GNU as. (Changed test cases:
eh-directive-pad.s and eh-directive-setfp.s)
llvm-svn: 183627
This commit is contained in:
Logan Chien
parent
89703c06f2
commit
325823a189
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@ -203,7 +203,7 @@ private:
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void Reset();
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void EmitPersonalityFixup(StringRef Name);
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void CollectUnwindOpcodes();
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void FlushPendingOffset();
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void FlushUnwindOpcodes(bool AllowCompactModel0);
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void SwitchToEHSection(const char *Prefix, unsigned Type, unsigned Flags,
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@ -221,13 +221,14 @@ private:
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MCSymbol *ExTab;
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MCSymbol *FnStart;
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const MCSymbol *Personality;
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uint32_t VFPRegSave; // Register mask for {d31-d0}
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uint32_t RegSave; // Register mask for {r15-r0}
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int64_t SPOffset;
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uint16_t FPReg;
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int64_t FPOffset;
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unsigned PersonalityIndex;
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unsigned FPReg; // Frame pointer register
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int64_t FPOffset; // Offset: (final frame pointer) - (initial $sp)
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int64_t SPOffset; // Offset: (final $sp) - (initial $sp)
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int64_t PendingOffset; // Offset: (final $sp) - (emitted $sp)
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bool UsedFP;
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bool CantUnwind;
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SmallVector<uint8_t, 64> Opcodes;
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UnwindOpcodeAssembler UnwindOpAsm;
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};
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} // end anonymous namespace
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@ -280,19 +281,18 @@ inline void ARMELFStreamer::SwitchToExIdxSection(const MCSymbol &FnStart) {
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}
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void ARMELFStreamer::Reset() {
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const MCRegisterInfo &MRI = getContext().getRegisterInfo();
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ExTab = NULL;
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FnStart = NULL;
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Personality = NULL;
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VFPRegSave = 0;
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RegSave = 0;
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FPReg = MRI.getEncodingValue(ARM::SP);
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PersonalityIndex = NUM_PERSONALITY_INDEX;
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FPReg = ARM::SP;
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FPOffset = 0;
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SPOffset = 0;
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PendingOffset = 0;
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UsedFP = false;
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CantUnwind = false;
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Opcodes.clear();
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UnwindOpAsm.Reset();
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}
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@ -312,18 +312,6 @@ void ARMELFStreamer::EmitPersonalityFixup(StringRef Name) {
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MCFixup::getKindForSize(4, false)));
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}
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void ARMELFStreamer::CollectUnwindOpcodes() {
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if (UsedFP) {
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UnwindOpAsm.EmitSetFP(FPReg);
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UnwindOpAsm.EmitSPOffset(-FPOffset);
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} else {
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UnwindOpAsm.EmitSPOffset(SPOffset);
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}
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UnwindOpAsm.EmitVFPRegSave(VFPRegSave);
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UnwindOpAsm.EmitRegSave(RegSave);
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UnwindOpAsm.Finalize();
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}
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void ARMELFStreamer::EmitFnStart() {
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assert(FnStart == 0);
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FnStart = getContext().CreateTempSymbol();
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@ -340,7 +328,6 @@ void ARMELFStreamer::EmitFnEnd() {
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// Emit the exception index table entry
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SwitchToExIdxSection(*FnStart);
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unsigned PersonalityIndex = UnwindOpAsm.getPersonalityIndex();
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if (PersonalityIndex < NUM_PERSONALITY_INDEX)
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EmitPersonalityFixup(GetAEABIUnwindPersonalityName(PersonalityIndex));
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@ -366,9 +353,10 @@ void ARMELFStreamer::EmitFnEnd() {
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// opcodes should always be 4 bytes.
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assert(PersonalityIndex == AEABI_UNWIND_CPP_PR0 &&
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"Compact model must use __aeabi_cpp_unwind_pr0 as personality");
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assert(UnwindOpAsm.size() == 4u &&
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assert(Opcodes.size() == 4u &&
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"Unwind opcode size for __aeabi_cpp_unwind_pr0 must be equal to 4");
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EmitBytes(UnwindOpAsm.data(), 0);
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EmitBytes(StringRef(reinterpret_cast<const char*>(Opcodes.data()),
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Opcodes.size()), 0);
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}
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// Switch to the section containing FnStart
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@ -382,15 +370,31 @@ void ARMELFStreamer::EmitCantUnwind() {
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CantUnwind = true;
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}
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void ARMELFStreamer::FlushPendingOffset() {
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if (PendingOffset != 0) {
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UnwindOpAsm.EmitSPOffset(-PendingOffset);
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PendingOffset = 0;
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}
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}
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void ARMELFStreamer::FlushUnwindOpcodes(bool AllowCompactModel0) {
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// Collect and finalize the unwind opcodes
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CollectUnwindOpcodes();
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// Emit the unwind opcode to restore $sp.
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if (UsedFP) {
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const MCRegisterInfo &MRI = getContext().getRegisterInfo();
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int64_t LastRegSaveSPOffset = SPOffset - PendingOffset;
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UnwindOpAsm.EmitSPOffset(LastRegSaveSPOffset - FPOffset);
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UnwindOpAsm.EmitSetSP(MRI.getEncodingValue(FPReg));
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} else {
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FlushPendingOffset();
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}
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// Finalize the unwind opcode sequence
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UnwindOpAsm.Finalize(PersonalityIndex, Opcodes);
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// For compact model 0, we have to emit the unwind opcodes in the .ARM.exidx
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// section. Thus, we don't have to create an entry in the .ARM.extab
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// section.
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if (AllowCompactModel0 &&
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UnwindOpAsm.getPersonalityIndex() == AEABI_UNWIND_CPP_PR0)
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if (AllowCompactModel0 && PersonalityIndex == AEABI_UNWIND_CPP_PR0)
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return;
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// Switch to .ARM.extab section.
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@ -412,7 +416,8 @@ void ARMELFStreamer::FlushUnwindOpcodes(bool AllowCompactModel0) {
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}
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// Emit unwind opcodes
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EmitBytes(UnwindOpAsm.data(), 0);
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EmitBytes(StringRef(reinterpret_cast<const char *>(Opcodes.data()),
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Opcodes.size()), 0);
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}
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void ARMELFStreamer::EmitHandlerData() {
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@ -427,42 +432,55 @@ void ARMELFStreamer::EmitPersonality(const MCSymbol *Per) {
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void ARMELFStreamer::EmitSetFP(unsigned NewFPReg,
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unsigned NewSPReg,
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int64_t Offset) {
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assert(SPOffset == 0 &&
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"Current implementation assumes .setfp precedes .pad");
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const MCRegisterInfo &MRI = getContext().getRegisterInfo();
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uint16_t NewFPRegEncVal = MRI.getEncodingValue(NewFPReg);
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#ifndef NDEBUG
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uint16_t NewSPRegEncVal = MRI.getEncodingValue(NewSPReg);
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#endif
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assert((NewSPReg == ARM::SP || NewSPRegEncVal == FPReg) &&
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assert((NewSPReg == ARM::SP || NewSPReg == FPReg) &&
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"the operand of .setfp directive should be either $sp or $fp");
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UsedFP = true;
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FPReg = NewFPRegEncVal;
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FPOffset = Offset;
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FPReg = NewFPReg;
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if (NewSPReg == ARM::SP)
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FPOffset = SPOffset + Offset;
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else
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FPOffset += Offset;
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}
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void ARMELFStreamer::EmitPad(int64_t Offset) {
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SPOffset += Offset;
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// Track the change of the $sp offset
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SPOffset -= Offset;
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// To squash multiple .pad directives, we should delay the unwind opcode
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// until the .save, .vsave, .handlerdata, or .fnend directives.
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PendingOffset -= Offset;
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}
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void ARMELFStreamer::EmitRegSave(const SmallVectorImpl<unsigned> &RegList,
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bool IsVector) {
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// Collect the registers in the register list
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unsigned Count = 0;
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uint32_t Mask = 0;
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const MCRegisterInfo &MRI = getContext().getRegisterInfo();
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#ifndef NDEBUG
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unsigned Max = IsVector ? 32 : 16;
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#endif
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uint32_t &RegMask = IsVector ? VFPRegSave : RegSave;
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for (size_t i = 0; i < RegList.size(); ++i) {
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unsigned Reg = MRI.getEncodingValue(RegList[i]);
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assert(Reg < Max && "Register encoded value out of range");
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RegMask |= 1u << Reg;
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assert(Reg < (IsVector ? 32 : 16) && "Register out of range");
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unsigned Bit = (1u << Reg);
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if ((Mask & Bit) == 0) {
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Mask |= Bit;
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++Count;
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}
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}
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// Track the change the $sp offset: For the .save directive, the
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// corresponding push instruction will decrease the $sp by (4 * Count).
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// For the .vsave directive, the corresponding vpush instruction will
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// decrease $sp by (8 * Count).
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SPOffset -= Count * (IsVector ? 8 : 4);
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// Emit the opcode
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FlushPendingOffset();
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if (IsVector)
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UnwindOpAsm.EmitVFPRegSave(Mask);
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else
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UnwindOpAsm.EmitRegSave(Mask);
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}
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namespace llvm {
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@ -20,6 +20,48 @@
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using namespace llvm;
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namespace {
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/// UnwindOpcodeStreamer - The simple wrapper over SmallVector to emit bytes
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/// with MSB to LSB per uint32_t ordering. For example, the first byte will
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/// be placed in Vec[3], and the following bytes will be placed in 2, 1, 0,
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/// 7, 6, 5, 4, 11, 10, 9, 8, and so on.
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class UnwindOpcodeStreamer {
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private:
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SmallVectorImpl<uint8_t> &Vec;
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size_t Pos;
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public:
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UnwindOpcodeStreamer(SmallVectorImpl<uint8_t> &V) : Vec(V), Pos(3) {
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}
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/// Emit the byte in MSB to LSB per uint32_t order.
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inline void EmitByte(uint8_t elem) {
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Vec[Pos] = elem;
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Pos = (((Pos ^ 0x3u) + 1) ^ 0x3u);
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}
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/// Emit the size prefix.
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inline void EmitSize(size_t Size) {
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size_t SizeInWords = (Size + 3) / 4;
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assert(SizeInWords <= 0x100u &&
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"Only 256 additional words are allowed for unwind opcodes");
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EmitByte(static_cast<uint8_t>(SizeInWords - 1));
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}
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/// Emit the personality index prefix.
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inline void EmitPersonalityIndex(unsigned PI) {
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assert(PI < NUM_PERSONALITY_INDEX && "Invalid personality prefix");
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EmitByte(EHT_COMPACT | PI);
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}
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/// Fill the rest of bytes with FINISH opcode.
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inline void FillFinishOpcode() {
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while (Pos < Vec.size())
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EmitByte(UNWIND_OPCODE_FINISH);
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}
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};
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}
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void UnwindOpcodeAssembler::EmitRegSave(uint32_t RegSave) {
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if (RegSave == 0u)
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return;
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@ -43,28 +85,22 @@ void UnwindOpcodeAssembler::EmitRegSave(uint32_t RegSave) {
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uint32_t UnmaskedReg = RegSave & 0xfff0u & (~Mask);
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if (UnmaskedReg == 0u) {
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// Pop r[4 : (4 + n)]
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Ops.push_back(UNWIND_OPCODE_POP_REG_RANGE_R4 | Range);
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EmitInt8(UNWIND_OPCODE_POP_REG_RANGE_R4 | Range);
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RegSave &= 0x000fu;
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} else if (UnmaskedReg == (1u << 14)) {
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// Pop r[14] + r[4 : (4 + n)]
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Ops.push_back(UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range);
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EmitInt8(UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range);
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RegSave &= 0x000fu;
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}
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}
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// Two bytes opcode to save register r15-r4
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if ((RegSave & 0xfff0u) != 0) {
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uint32_t Op = UNWIND_OPCODE_POP_REG_MASK_R4 | (RegSave >> 4);
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Ops.push_back(static_cast<uint8_t>(Op >> 8));
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Ops.push_back(static_cast<uint8_t>(Op & 0xff));
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}
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if ((RegSave & 0xfff0u) != 0)
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EmitInt16(UNWIND_OPCODE_POP_REG_MASK_R4 | (RegSave >> 4));
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// Opcode to save register r3-r0
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if ((RegSave & 0x000fu) != 0) {
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uint32_t Op = UNWIND_OPCODE_POP_REG_MASK | (RegSave & 0x000fu);
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Ops.push_back(static_cast<uint8_t>(Op >> 8));
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Ops.push_back(static_cast<uint8_t>(Op & 0xff));
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}
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if ((RegSave & 0x000fu) != 0)
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EmitInt16(UNWIND_OPCODE_POP_REG_MASK | (RegSave & 0x000fu));
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}
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/// Emit unwind opcodes for .vsave directives
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@ -89,10 +125,8 @@ void UnwindOpcodeAssembler::EmitVFPRegSave(uint32_t VFPRegSave) {
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Bit >>= 1;
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}
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uint32_t Op =
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UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD_D16 | ((i - 16) << 4) | Range;
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Ops.push_back(static_cast<uint8_t>(Op >> 8));
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Ops.push_back(static_cast<uint8_t>(Op & 0xff));
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EmitInt16(UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD_D16 |
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((i - 16) << 4) | Range);
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}
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while (i > 0) {
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@ -113,86 +147,75 @@ void UnwindOpcodeAssembler::EmitVFPRegSave(uint32_t VFPRegSave) {
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Bit >>= 1;
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}
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uint32_t Op = UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD | (i << 4) | Range;
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Ops.push_back(static_cast<uint8_t>(Op >> 8));
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Ops.push_back(static_cast<uint8_t>(Op & 0xff));
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EmitInt16(UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD | (i << 4) | Range);
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}
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}
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/// Emit unwind opcodes for .setfp directives
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void UnwindOpcodeAssembler::EmitSetFP(uint16_t FPReg) {
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Ops.push_back(UNWIND_OPCODE_SET_VSP | FPReg);
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/// Emit unwind opcodes to copy address from source register to $sp.
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void UnwindOpcodeAssembler::EmitSetSP(uint16_t Reg) {
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EmitInt8(UNWIND_OPCODE_SET_VSP | Reg);
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}
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/// Emit unwind opcodes to update stack pointer
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/// Emit unwind opcodes to add $sp with an offset.
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void UnwindOpcodeAssembler::EmitSPOffset(int64_t Offset) {
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if (Offset > 0x200) {
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uint8_t Buff[10];
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size_t Size = encodeULEB128((Offset - 0x204) >> 2, Buff);
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Ops.push_back(UNWIND_OPCODE_INC_VSP_ULEB128);
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Ops.append(Buff, Buff + Size);
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uint8_t Buff[16];
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Buff[0] = UNWIND_OPCODE_INC_VSP_ULEB128;
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size_t ULEBSize = encodeULEB128((Offset - 0x204) >> 2, Buff + 1);
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EmitBytes(Buff, ULEBSize + 1);
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} else if (Offset > 0) {
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if (Offset > 0x100) {
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Ops.push_back(UNWIND_OPCODE_INC_VSP | 0x3fu);
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EmitInt8(UNWIND_OPCODE_INC_VSP | 0x3fu);
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Offset -= 0x100;
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}
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Ops.push_back(UNWIND_OPCODE_INC_VSP |
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static_cast<uint8_t>((Offset - 4) >> 2));
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EmitInt8(UNWIND_OPCODE_INC_VSP | static_cast<uint8_t>((Offset - 4) >> 2));
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} else if (Offset < 0) {
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while (Offset < -0x100) {
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Ops.push_back(UNWIND_OPCODE_DEC_VSP | 0x3fu);
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EmitInt8(UNWIND_OPCODE_DEC_VSP | 0x3fu);
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Offset += 0x100;
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}
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Ops.push_back(UNWIND_OPCODE_DEC_VSP |
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static_cast<uint8_t>(((-Offset) - 4) >> 2));
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EmitInt8(UNWIND_OPCODE_DEC_VSP |
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static_cast<uint8_t>(((-Offset) - 4) >> 2));
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}
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}
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void UnwindOpcodeAssembler::AddOpcodeSizePrefix(size_t Pos) {
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size_t SizeInWords = (size() + 3) / 4;
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assert(SizeInWords <= 0x100u &&
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"Only 256 additional words are allowed for unwind opcodes");
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Ops[Pos] = static_cast<uint8_t>(SizeInWords - 1);
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}
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void UnwindOpcodeAssembler::Finalize(unsigned &PersonalityIndex,
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SmallVectorImpl<uint8_t> &Result) {
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void UnwindOpcodeAssembler::AddPersonalityIndexPrefix(size_t Pos, unsigned PI) {
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assert(PI < NUM_PERSONALITY_INDEX && "Invalid personality prefix");
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Ops[Pos] = EHT_COMPACT | PI;
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}
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UnwindOpcodeStreamer OpStreamer(Result);
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void UnwindOpcodeAssembler::EmitFinishOpcodes() {
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for (size_t i = (0x4u - (size() & 0x3u)) & 0x3u; i > 0; --i)
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Ops.push_back(UNWIND_OPCODE_FINISH);
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}
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void UnwindOpcodeAssembler::Finalize() {
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if (HasPersonality) {
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// Personality specified by .personality directive
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Offset = 1;
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AddOpcodeSizePrefix(1);
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// User-specifed personality routine: [ SIZE , OP1 , OP2 , ... ]
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PersonalityIndex = NUM_PERSONALITY_INDEX;
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size_t TotalSize = Ops.size() + 1;
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size_t RoundUpSize = (TotalSize + 3) / 4 * 4;
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Result.resize(RoundUpSize);
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OpStreamer.EmitSize(RoundUpSize);
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} else {
|
||||
if (getOpcodeSize() <= 3) {
|
||||
if (Ops.size() <= 3) {
|
||||
// __aeabi_unwind_cpp_pr0: [ 0x80 , OP1 , OP2 , OP3 ]
|
||||
Offset = 1;
|
||||
PersonalityIndex = AEABI_UNWIND_CPP_PR0;
|
||||
AddPersonalityIndexPrefix(Offset, PersonalityIndex);
|
||||
Result.resize(4);
|
||||
OpStreamer.EmitPersonalityIndex(PersonalityIndex);
|
||||
} else {
|
||||
// __aeabi_unwind_cpp_pr1: [ 0x81 , SIZE , OP1 , OP2 , ... ]
|
||||
Offset = 0;
|
||||
PersonalityIndex = AEABI_UNWIND_CPP_PR1;
|
||||
AddPersonalityIndexPrefix(Offset, PersonalityIndex);
|
||||
AddOpcodeSizePrefix(1);
|
||||
size_t TotalSize = Ops.size() + 2;
|
||||
size_t RoundUpSize = (TotalSize + 3) / 4 * 4;
|
||||
Result.resize(RoundUpSize);
|
||||
OpStreamer.EmitPersonalityIndex(PersonalityIndex);
|
||||
OpStreamer.EmitSize(RoundUpSize);
|
||||
}
|
||||
}
|
||||
|
||||
// Emit the padding finish opcodes if the size() is not multiple of 4.
|
||||
EmitFinishOpcodes();
|
||||
// Copy the unwind opcodes
|
||||
for (size_t i = OpBegins.size() - 1; i > 0; --i)
|
||||
for (size_t j = OpBegins[i - 1], end = OpBegins[i]; j < end; ++j)
|
||||
OpStreamer.EmitByte(Ops[j]);
|
||||
|
||||
// Swap the byte order
|
||||
uint8_t *Ptr = Ops.begin() + Offset;
|
||||
assert(size() % 4 == 0 && "Final unwind opcodes should align to 4");
|
||||
for (size_t i = 0, n = size(); i < n; i += 4) {
|
||||
std::swap(Ptr[i], Ptr[i + 3]);
|
||||
std::swap(Ptr[i + 1], Ptr[i + 2]);
|
||||
}
|
||||
// Emit the padding finish opcodes if the size is not multiple of 4.
|
||||
OpStreamer.FillFinishOpcode();
|
||||
|
||||
// Reset the assembler state
|
||||
Reset();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,86 +27,61 @@ class MCSymbol;
|
|||
|
||||
class UnwindOpcodeAssembler {
|
||||
private:
|
||||
llvm::SmallVector<uint8_t, 8> Ops;
|
||||
|
||||
unsigned Offset;
|
||||
unsigned PersonalityIndex;
|
||||
llvm::SmallVector<uint8_t, 32> Ops;
|
||||
llvm::SmallVector<unsigned, 8> OpBegins;
|
||||
bool HasPersonality;
|
||||
|
||||
enum {
|
||||
// The number of bytes to be preserved for the size and personality index
|
||||
// prefix of unwind opcodes.
|
||||
NUM_PRESERVED_PREFIX_BUF = 2
|
||||
};
|
||||
|
||||
public:
|
||||
UnwindOpcodeAssembler()
|
||||
: Ops(NUM_PRESERVED_PREFIX_BUF), Offset(NUM_PRESERVED_PREFIX_BUF),
|
||||
PersonalityIndex(NUM_PERSONALITY_INDEX), HasPersonality(0) {
|
||||
: HasPersonality(0) {
|
||||
OpBegins.push_back(0);
|
||||
}
|
||||
|
||||
/// Reset the unwind opcode assembler.
|
||||
void Reset() {
|
||||
Ops.resize(NUM_PRESERVED_PREFIX_BUF);
|
||||
Offset = NUM_PRESERVED_PREFIX_BUF;
|
||||
PersonalityIndex = NUM_PERSONALITY_INDEX;
|
||||
Ops.clear();
|
||||
OpBegins.clear();
|
||||
OpBegins.push_back(0);
|
||||
HasPersonality = 0;
|
||||
}
|
||||
|
||||
/// Get the size of the payload (including the size byte)
|
||||
size_t size() const {
|
||||
return Ops.size() - Offset;
|
||||
}
|
||||
|
||||
/// Get the beginning of the payload
|
||||
const uint8_t *begin() const {
|
||||
return Ops.begin() + Offset;
|
||||
}
|
||||
|
||||
/// Get the payload
|
||||
StringRef data() const {
|
||||
return StringRef(reinterpret_cast<const char *>(begin()), size());
|
||||
}
|
||||
|
||||
/// Set the personality index
|
||||
void setPersonality(const MCSymbol *Per) {
|
||||
HasPersonality = 1;
|
||||
}
|
||||
|
||||
/// Get the personality index
|
||||
unsigned getPersonalityIndex() const {
|
||||
return PersonalityIndex;
|
||||
}
|
||||
|
||||
/// Emit unwind opcodes for .save directives
|
||||
void EmitRegSave(uint32_t RegSave);
|
||||
|
||||
/// Emit unwind opcodes for .vsave directives
|
||||
void EmitVFPRegSave(uint32_t VFPRegSave);
|
||||
|
||||
/// Emit unwind opcodes for .setfp directives
|
||||
void EmitSetFP(uint16_t FPReg);
|
||||
/// Emit unwind opcodes to copy address from source register to $sp.
|
||||
void EmitSetSP(uint16_t Reg);
|
||||
|
||||
/// Emit unwind opcodes to update stack pointer
|
||||
/// Emit unwind opcodes to add $sp with an offset.
|
||||
void EmitSPOffset(int64_t Offset);
|
||||
|
||||
/// Finalize the unwind opcode sequence for EmitBytes()
|
||||
void Finalize();
|
||||
void Finalize(unsigned &PersonalityIndex,
|
||||
SmallVectorImpl<uint8_t> &Result);
|
||||
|
||||
private:
|
||||
/// Get the size of the opcodes in bytes.
|
||||
size_t getOpcodeSize() const {
|
||||
return Ops.size() - NUM_PRESERVED_PREFIX_BUF;
|
||||
void EmitInt8(unsigned Opcode) {
|
||||
Ops.push_back(Opcode & 0xff);
|
||||
OpBegins.push_back(OpBegins.back() + 1);
|
||||
}
|
||||
|
||||
/// Add the length prefix to the payload
|
||||
void AddOpcodeSizePrefix(size_t Pos);
|
||||
void EmitInt16(unsigned Opcode) {
|
||||
Ops.push_back((Opcode >> 8) & 0xff);
|
||||
Ops.push_back(Opcode & 0xff);
|
||||
OpBegins.push_back(OpBegins.back() + 2);
|
||||
}
|
||||
|
||||
/// Add personality index prefix in some compact format
|
||||
void AddPersonalityIndexPrefix(size_t Pos, unsigned PersonalityIndex);
|
||||
|
||||
/// Fill the words with finish opcode if it is not aligned
|
||||
void EmitFinishOpcodes();
|
||||
void EmitBytes(const uint8_t *Opcode, size_t Size) {
|
||||
Ops.insert(Ops.end(), Opcode, Opcode + Size);
|
||||
OpBegins.push_back(OpBegins.back() + Size);
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace llvm
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ declare void @_ZSt9terminatev()
|
|||
|
||||
; CHECK: section .test_section
|
||||
; CHECK: section .ARM.extab.test_section
|
||||
; CHECK-NEXT: 0000 00000000 c9409b01 b0818484
|
||||
; CHECK-NEXT: 0000 00000000 c94a9b01 b0818484
|
||||
; CHECK: section .ARM.exidx.test_section
|
||||
; CHECK-NEXT: 0000 00000000 00000000
|
||||
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ declare void @_ZSt9terminatev()
|
|||
|
||||
; CHECK: section .text
|
||||
; CHECK: section .ARM.extab
|
||||
; CHECK-NEXT: 0000 00000000 c9409b01 b0818484
|
||||
; CHECK-NEXT: 0000 00000000 c94a9b01 b0818484
|
||||
; CHECK: section .ARM.exidx
|
||||
; CHECK-NEXT: 0000 00000000 00000000
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,93 @@
|
|||
@ Integrated test for ARM unwind directive parser and assembler.
|
||||
|
||||
@ This is a simplified real world test case generated from this C++ code
|
||||
@ (with and without -fomit-frame-pointer)
|
||||
@
|
||||
@ extern void print(int, int, int, int, int);
|
||||
@ extern void print(double, double, double, double, double);
|
||||
@
|
||||
@ void test(int a, int b, int c, int d, int e,
|
||||
@ double m, double n, double p, double q, double r) {
|
||||
@ try {
|
||||
@ print(a, b, c, d, e);
|
||||
@ } catch (...) {
|
||||
@ print(m, n, p, q, r);
|
||||
@ }
|
||||
@ }
|
||||
@
|
||||
@ This test case should check the unwind opcode to adjust the opcode and
|
||||
@ restore the general-purpose and VFP registers.
|
||||
|
||||
|
||||
@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
|
||||
@ RUN: | llvm-readobj -s -sd | FileCheck %s
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Assembly without frame pointer elimination
|
||||
@-------------------------------------------------------------------------------
|
||||
.syntax unified
|
||||
.section .TEST1
|
||||
.globl func1
|
||||
.align 2
|
||||
.type func1,%function
|
||||
func1:
|
||||
.fnstart
|
||||
.save {r4, r11, lr}
|
||||
push {r4, r11, lr}
|
||||
.setfp r11, sp, #4
|
||||
add r11, sp, #4
|
||||
.vsave {d8, d9, d10, d11, d12}
|
||||
vpush {d8, d9, d10, d11, d12}
|
||||
.pad #28
|
||||
sub sp, sp, #28
|
||||
sub sp, r11, #44
|
||||
vpop {d8, d9, d10, d11, d12}
|
||||
pop {r4, r11, pc}
|
||||
.Ltmp1:
|
||||
.size func1, .Ltmp1-func1
|
||||
.globl __gxx_personality_v0
|
||||
.personality __gxx_personality_v0
|
||||
.handlerdata
|
||||
.fnend
|
||||
|
||||
@ CHECK: Section {
|
||||
@ CHECK: Name: .ARM.extab.TEST1
|
||||
@ CHECK: SectionData (
|
||||
@ CHECK: 0000: 00000000 C94A9B01 B0818484 |.....J......|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Assembly with frame pointer elimination
|
||||
@-------------------------------------------------------------------------------
|
||||
.section .TEST2
|
||||
.globl func2
|
||||
.align 2
|
||||
.type func2,%function
|
||||
func2:
|
||||
.fnstart
|
||||
.save {r4, lr}
|
||||
push {r4, lr}
|
||||
.vsave {d8, d9, d10, d11, d12}
|
||||
vpush {d8, d9, d10, d11, d12}
|
||||
.pad #24
|
||||
sub sp, sp, #24
|
||||
add sp, sp, #24
|
||||
vpop {d8, d9, d10, d11, d12}
|
||||
pop {r4, pc}
|
||||
.Ltmp2:
|
||||
.size func2, .Ltmp2-func2
|
||||
.globl __gxx_personality_v0
|
||||
.personality __gxx_personality_v0
|
||||
.handlerdata
|
||||
.fnend
|
||||
|
||||
@ CHECK: Section {
|
||||
@ CHECK: Name: .ARM.extab.TEST2
|
||||
@ CHECK: SectionData (
|
||||
@ CHECK: 0000: 00000000 84C90501 B0B0B0A8 |............|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
|
||||
@ RUN: | llvm-readobj -s -sd | FileCheck %s
|
||||
|
||||
@ Check for different combination of .setfp, .pad, .save and .vsave.
|
||||
|
||||
.syntax unified
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ TEST1: Check .pad before .setfp directive.
|
||||
@-------------------------------------------------------------------------------
|
||||
.section .TEST1
|
||||
.globl func1
|
||||
.type func1,%function
|
||||
.align 2
|
||||
.fnstart
|
||||
func1:
|
||||
.pad #12
|
||||
sub sp, sp, #12
|
||||
.setfp fp, sp, #8
|
||||
add fp, sp, #8
|
||||
sub sp, fp, #8
|
||||
add sp, sp, #12
|
||||
bx lr
|
||||
.personality __gxx_personality_v0
|
||||
.handlerdata
|
||||
.fnend
|
||||
|
||||
@ CHECK: Section {
|
||||
@ CHECK: Name: .ARM.extab.TEST1
|
||||
@ CHECK: SectionData (
|
||||
@ CHECK: 0000: 00000000 B0009B00 |........|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ TEST2: Check .pad after .setfp directive.
|
||||
@-------------------------------------------------------------------------------
|
||||
.section .TEST2
|
||||
.globl func2
|
||||
.type func2,%function
|
||||
.align 2
|
||||
.fnstart
|
||||
func2:
|
||||
.setfp fp, sp, #8
|
||||
add fp, sp, #8
|
||||
.pad #12
|
||||
sub sp, sp, #12
|
||||
add sp, sp, #12
|
||||
sub sp, fp, #8
|
||||
bx lr
|
||||
.personality __gxx_personality_v0
|
||||
.handlerdata
|
||||
.fnend
|
||||
|
||||
@ CHECK: Section {
|
||||
@ CHECK: Name: .ARM.extab.TEST2
|
||||
@ CHECK: SectionData (
|
||||
@ CHECK: 0000: 00000000 B0419B00 |.....A..|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ TEST3: Check .setfp, .pad, .setfp directive.
|
||||
@-------------------------------------------------------------------------------
|
||||
.section .TEST3
|
||||
.globl func3
|
||||
.type func3,%function
|
||||
.align 2
|
||||
.fnstart
|
||||
func3:
|
||||
@ prologue:
|
||||
.setfp fp, sp, #4
|
||||
add fp, sp, #4
|
||||
.pad #8
|
||||
sub sp, sp, #8
|
||||
.setfp fp, sp, #4
|
||||
add fp, sp, #4
|
||||
|
||||
@ epilogue:
|
||||
add sp, fp, #4
|
||||
bx lr
|
||||
.personality __gxx_personality_v0
|
||||
.handlerdata
|
||||
.fnend
|
||||
|
||||
@ CHECK: Section {
|
||||
@ CHECK: Name: .ARM.extab.TEST3
|
||||
@ CHECK: SectionData (
|
||||
@ CHECK: 0000: 00000000 B0009B00 |........|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ TEST4: Check ".setfp fp, sp" and ".setfp fp, fp" directive.
|
||||
@-------------------------------------------------------------------------------
|
||||
.section .TEST4
|
||||
.globl func4
|
||||
.type func4,%function
|
||||
.align 2
|
||||
.fnstart
|
||||
func4:
|
||||
@ prologue:
|
||||
.setfp fp, sp, #8
|
||||
add fp, sp, #8
|
||||
.setfp fp, fp, #8
|
||||
add fp, fp, #8
|
||||
|
||||
@ epilogue:
|
||||
sub sp, fp, #16
|
||||
bx lr
|
||||
.personality __gxx_personality_v0
|
||||
.handlerdata
|
||||
.fnend
|
||||
|
||||
@ CHECK: Section {
|
||||
@ CHECK: Name: .ARM.extab.TEST4
|
||||
@ CHECK: SectionData (
|
||||
@ CHECK: 0000: 00000000 B0439B00 |.....C..|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ TEST5: Check .setfp, .save, .setfp directive.
|
||||
@-------------------------------------------------------------------------------
|
||||
.section .TEST5
|
||||
.globl func5
|
||||
.type func5,%function
|
||||
.align 2
|
||||
.fnstart
|
||||
func5:
|
||||
@ prologue:
|
||||
.setfp fp, sp, #16
|
||||
add fp, sp, #16
|
||||
.save {r4, r5, r6, r7, r8}
|
||||
push {r4, r5, r6, r7, r8}
|
||||
.pad #8
|
||||
add sp, sp, #8
|
||||
.pad #8
|
||||
sub sp, sp, #8
|
||||
.save {r9, r10}
|
||||
push {r9, r10}
|
||||
.setfp fp, sp, #24
|
||||
add fp, sp, #24
|
||||
|
||||
@ epilogue:
|
||||
sub sp, fp, #24
|
||||
pop {r9, r10}
|
||||
add sp, sp, #16
|
||||
pop {r4, r5, r6, r7, r8}
|
||||
bx lr
|
||||
.personality __gxx_personality_v0
|
||||
.handlerdata
|
||||
.fnend
|
||||
|
||||
@ CHECK: Section {
|
||||
@ CHECK: Name: .ARM.extab.TEST5
|
||||
@ CHECK: SectionData (
|
||||
@ CHECK: 0000: 00000000 80459B01 B0A40360 |.....E.....`|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
|
@ -121,7 +121,7 @@ func3b:
|
|||
@ CHECK: Section {
|
||||
@ CHECK: Name: .ARM.extab.TEST3
|
||||
@ CHECK: SectionData (
|
||||
@ CHECK: 0000: 00000000 B0003F00 00000000 B03F3F00 |......?......??.|
|
||||
@ CHECK: 0000: 00000000 B03F0000 00000000 B03F3F00 |.....?.......??.|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
||||
|
|
@ -220,7 +220,7 @@ func5c:
|
|||
@ CHECK: Section {
|
||||
@ CHECK: Name: .ARM.extab.TEST5
|
||||
@ CHECK: SectionData (
|
||||
@ CHECK: 0000: 00000000 B0B04000 00000000 B0407F00 |......@......@..|
|
||||
@ CHECK: 0010: 00000000 407F7F00 |....@...|
|
||||
@ CHECK: 0000: 00000000 B0B04000 00000000 B07F4000 |......@.......@.|
|
||||
@ CHECK: 0010: 00000000 7F7F4000 |......@.|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
|
|
|||
|
|
@ -296,3 +296,48 @@ func4e:
|
|||
@ CHECK: 0020: 00000000 B00E8400 |........|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ TEST5
|
||||
@-------------------------------------------------------------------------------
|
||||
.section .TEST5
|
||||
.globl func5a
|
||||
.align 2
|
||||
.type func5a,%function
|
||||
.fnstart
|
||||
func5a:
|
||||
.save {r0, r1, r2, r3, r4, r5, r6}
|
||||
push {r0, r1, r2, r3, r4, r5, r6}
|
||||
pop {r0, r1, r2, r3, r4, r5, r6}
|
||||
bx lr
|
||||
.personality __gxx_personality_v0
|
||||
.handlerdata
|
||||
.fnend
|
||||
|
||||
.globl func5b
|
||||
.align 2
|
||||
.type func5b,%function
|
||||
.fnstart
|
||||
func5b:
|
||||
.save {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
|
||||
push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
|
||||
pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
|
||||
bx lr
|
||||
.personality __gxx_personality_v0
|
||||
.handlerdata
|
||||
.fnend
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Check the order of unwind opcode to pop registers.
|
||||
@ 0xB10F "pop {r0-r3}" should be emitted before 0xA2 "pop {r4-r6}".
|
||||
@ 0xB10F "pop {r0-r3}" should be emitted before 0x85FF "pop {r4-r12, r14}".
|
||||
@-------------------------------------------------------------------------------
|
||||
@ CHECK: Section {
|
||||
@ CHECK: Name: .ARM.extab.TEST5
|
||||
@ CHECK: SectionData (
|
||||
@ CHECK: 0000: 00000000 A20FB100 00000000 850FB101 |................|
|
||||
@ CHECK: 0010: B0B0B0FF |....|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
|
|
|||
|
|
@ -131,7 +131,7 @@ func3b:
|
|||
@ CHECK: Section {
|
||||
@ CHECK: Name: .ARM.extab.TEST3
|
||||
@ CHECK: SectionData (
|
||||
@ CHECK: 0000: 00000000 003F9B00 00000000 3F3F9B00 |.....?......??..|
|
||||
@ CHECK: 0000: 00000000 3F009B00 00000000 3F3F9B00 |....?.......??..|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
||||
|
|
@ -233,7 +233,7 @@ func5c:
|
|||
@ CHECK: Section {
|
||||
@ CHECK: Name: .ARM.extab.TEST5
|
||||
@ CHECK: SectionData (
|
||||
@ CHECK: 0000: 00000000 B0409B00 00000000 407F9B00 |.....@......@...|
|
||||
@ CHECK: 0010: 00000000 7F7F9B01 B0B0B040 |...........@|
|
||||
@ CHECK: 0000: 00000000 B0409B00 00000000 7F409B00 |.....@.......@..|
|
||||
@ CHECK: 0010: 00000000 7F409B01 B0B0B07F |.....@......|
|
||||
@ CHECK: )
|
||||
@ CHECK: }
|
||||
|
|
|
|||
Loading…
Reference in New Issue