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A select between a constant and zero, when fed by a bit test, can be efficiently 

lowered using a series of shifts.
Fixes <rdar://problem/8285015>.

llvm-svn: 114599
This commit is contained in:
Owen Anderson 2010-09-22 22:58:22 +00:00
parent bbb9287080
commit 3231d13ddd
2 changed files with 42 additions and 0 deletions
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29
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -6808,6 +6808,35 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
}
}
// fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
// where y is has a single bit set.
// A plaintext description would be, we can turn the SELECT_CC into an AND
// when the condition can be materialized as an all-ones register. Any
// single bit-test can be materialized as an all-ones register with
// shift-left and shift-right-arith.
if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
N0->getValueType(0) == VT &&
N1C && N1C->isNullValue() &&
N2C && N2C->isNullValue()) {
SDValue AndLHS = N0->getOperand(0);
ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
// Shift the tested bit over the sign bit.
APInt AndMask = ConstAndRHS->getAPIntValue();
SDValue ShlAmt =
DAG.getConstant(AndMask.countLeadingZeros(), getShiftAmountTy());
SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
// Now arithmetic right shift it all the way over, so the result is either
// all-ones, or zero.
SDValue ShrAmt =
DAG.getConstant(AndMask.getBitWidth()-1, getShiftAmountTy());
SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
}
}
// fold select C, 16, 0 -> shl C, 4
if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {

13
llvm/test/CodeGen/X86/bit-test-shift.ll Normal file
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@ -0,0 +1,13 @@
; RUN: llc < %s -march=x86 | FileCheck %s
; <rdar://problem/8285015>
define i32 @x(i32 %t) nounwind readnone ssp {
entry:
; CHECK: shll $23, %eax
; CHECK: sarl $31, %eax
; CHECK: andl $-26, %eax
%and = and i32 %t, 256
%tobool = icmp eq i32 %and, 0
%retval.0 = select i1 %tobool, i32 0, i32 -26
ret i32 %retval.0
}