Specify an asm string and operands lists for a bunch of instructions.
This only really covers no-operand instructions so far. llvm-svn: 15387
This commit is contained in:
Chris Lattner
parent
1c4ae85035
commit
321763358b
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@ -108,6 +108,12 @@ class Imp<list<Register> uses, list<Register> defs> {
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list<Register> Defs = defs;
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}
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// II - InstructionInfo - this will eventually replace the I class.
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class II<dag ops, string AsmStr> {
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dag OperandList = ops;
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string AsmString = AsmStr;
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}
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// Prefix byte classes which are used to indicate to the ad-hoc machine code
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// emitter that various prefix bytes are required.
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@ -148,15 +154,14 @@ class Im32i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm8>;
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// Helper for shift instructions
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class UsesCL { list<Register> Uses = [CL]; bit printImplicitUsesAfter = 1; }
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class PrintImpDefsAfter {bit printImplicitDefsAfter = 1;}
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//===----------------------------------------------------------------------===//
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// Instruction list...
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//
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def PHI : I<"PHI", 0, Pseudo>; // PHI node...
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def NOOP : I<"nop", 0x90, RawFrm>; // nop
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def PHI : I<"PHI", 0, Pseudo>; // PHI node...
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def NOOP : I<"nop", 0x90, RawFrm>, // nop
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II<(ops), "nop">;
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def ADJCALLSTACKDOWN : I<"ADJCALLSTACKDOWN", 0, Pseudo>;
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def ADJCALLSTACKUP : I<"ADJCALLSTACKUP", 0, Pseudo>;
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@ -172,7 +177,8 @@ let isTerminator = 1 in
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// Return instruction...
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let isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def RET : I<"ret", 0xC3, RawFrm>;
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def RET : I<"ret", 0xC3, RawFrm>,
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II<(ops), "ret">;
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// All branches are RawFrm, Void, Branch, and Terminators
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let isBranch = 1, isTerminator = 1 in
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@ -209,7 +215,8 @@ let isCall = 1 in
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions...
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//
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def LEAVE : I<"leave", 0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>;
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def LEAVE : I<"leave", 0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>,
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II<(ops), "leave">;
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def POP32r : I<"pop", 0x58, AddRegFrm>, Imp<[ESP],[ESP]>;
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let isTwoAddress = 1 in // R32 = bswap R32
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@ -230,27 +237,34 @@ def LEA32r : Im32<"lea", 0x8D, MRMSrcMem>; // R32 = lea [mem]
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def REP_MOVSB : I<"rep movsb", 0xA4, RawFrm>, REP,
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Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
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Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>,
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II<(ops), "rep movsb">;
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def REP_MOVSW : I<"rep movsw", 0xA5, RawFrm>, REP, OpSize,
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Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
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Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>,
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II<(ops), "rep movsw">;
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def REP_MOVSD : I<"rep movsd", 0xA5, RawFrm>, REP,
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Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
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Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>,
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II<(ops), "rep movsd">;
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def REP_STOSB : I<"rep stosb", 0xAA, RawFrm>, REP,
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Imp<[AL,ECX,EDI], [ECX,EDI]>;
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Imp<[AL,ECX,EDI], [ECX,EDI]>,
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II<(ops), "rep stosb">;
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def REP_STOSW : I<"rep stosw", 0xAB, RawFrm>, REP, OpSize,
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Imp<[AX,ECX,EDI], [ECX,EDI]>;
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Imp<[AX,ECX,EDI], [ECX,EDI]>,
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II<(ops), "rep stosw">;
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def REP_STOSD : I<"rep stosd", 0xAB, RawFrm>, REP,
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Imp<[EAX,ECX,EDI], [ECX,EDI]>;
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Imp<[EAX,ECX,EDI], [ECX,EDI]>,
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II<(ops), "rep stosd">;
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//===----------------------------------------------------------------------===//
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// Input/Output Instructions...
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//
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let printImplicitUsesAfter = 1, printImplicitDefsAfter = 1 in {
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def IN8rr : I<"in", 0xEC, RawFrm>, Imp<[DX], [AL]>; // AL = in I/O address DX
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def IN16rr : I<"in", 0xED, RawFrm>, Imp<[DX], [AX]>, OpSize; // AX = in I/O address DX
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def IN32rr : I<"in", 0xED, RawFrm>, Imp<[DX],[EAX]>; // EAX = in I/O address DX
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}
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def IN8rr : I<"in", 0xEC, RawFrm>, Imp<[DX], [AL]>, // AL = in I/O address DX
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II<(ops), "in AL, DX">;
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def IN16rr : I<"in", 0xED, RawFrm>, Imp<[DX], [AX]>, OpSize, // AX = in I/O address DX
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II<(ops), "in AX, DX">;
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def IN32rr : I<"in", 0xED, RawFrm>, Imp<[DX],[EAX]>, // EAX = in I/O address DX
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II<(ops), "in EAX, DX">;
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let printImplicitDefsBefore = 1 in {
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def IN8ri : Ii16<"in", 0xE4, RawFrm>, Imp<[], [AL]>; // AL = in [I/O address]
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@ -259,9 +273,12 @@ let printImplicitDefsBefore = 1 in {
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}
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let printImplicitUsesAfter = 1 in {
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def OUT8rr : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>;
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def OUT16rr : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize;
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def OUT32rr : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>;
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def OUT8rr : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>,
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II<(ops), "out DX, AL">;
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def OUT16rr : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize,
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II<(ops), "out DX, AX">;
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def OUT32rr : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>,
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II<(ops), "out DX, EAX">;
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def OUT8ir : Ii16<"out", 0xE6, RawFrm>, Imp<[AL], []>;
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def OUT16ir : Ii16<"out", 0xE7, RawFrm>, Imp<[AX], []>, OpSize;
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def OUT32ir : Ii16<"out", 0xE7, RawFrm>, Imp<[EAX], []>;
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@ -317,9 +334,12 @@ def IDIV16m: Im16<"idiv",0xF7, MRM7m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[m
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def IDIV32m: Im32<"idiv",0xF7, MRM7m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
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// Sign-extenders for division
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def CBW : I<"cbw", 0x98, RawFrm >, Imp<[AL],[AH]>; // AX = signext(AL)
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def CWD : I<"cwd", 0x99, RawFrm >, Imp<[AX],[DX]>; // DX:AX = signext(AX)
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def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
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def CBW : I<"cbw", 0x98, RawFrm >, Imp<[AL],[AH]>, // AX = signext(AL)
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II<(ops), "cbw">;
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def CWD : I<"cwd", 0x99, RawFrm >, Imp<[AX],[DX]>, // DX:AX = signext(AX)
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II<(ops), "cwd">;
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def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>, // EDX:EAX = signext(EAX)
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II<(ops), "cdq">;
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//===----------------------------------------------------------------------===//
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// Two address Instructions...
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@ -417,7 +437,8 @@ def DEC16m : Im16<"dec", 0xFF, MRM1m>, OpSize; // --[mem16]
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def DEC32m : Im32<"dec", 0xFF, MRM1m>; // --[mem32]
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// Logical operators...
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def AND8rr : I <"and", 0x20, MRMDestReg>;
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def AND8rr : I <"and", 0x20, MRMDestReg>,
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II<(ops R8:$dst, R8:$src1, R8:$src2), "and $dst, $src2">;
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def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize;
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def AND32rr : I <"and", 0x21, MRMDestReg>;
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def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8
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@ -487,9 +508,12 @@ def XOR32mi8 : Im32i8<"xor", 0x83, MRM6m >; // [mem32] ^= imm8
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// Shift instructions
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// FIXME: provide shorter instructions when imm8 == 1
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def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL; // R8 <<= cl
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def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL; // R16 <<= cl
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def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL; // R32 <<= cl
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def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL, // R8 <<= cl
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II<(ops R8:$dst, R8:$src), "shl $dst, CL">;
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def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL, // R16 <<= cl
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II<(ops R16:$dst, R16:$src), "shl $dst, CL">;
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def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL, // R32 <<= cl
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II<(ops R32:$dst, R32:$src), "shl $dst, CL">;
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def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > , UsesCL; // [mem8] <<= cl
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def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize, UsesCL; // [mem16] <<= cl
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def SHL32mCL : Im32 <"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl
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@ -501,9 +525,12 @@ def SHL8mi : Im8i8 <"shl", 0xC0, MRM4m >; // [mem8] <<= i
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def SHL16mi : Im16i8<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8
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def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8
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def SHR8rCL : I <"shr", 0xD2, MRM5r > , UsesCL; // R8 >>= cl
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def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, UsesCL; // R16 >>= cl
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def SHR32rCL : I <"shr", 0xD3, MRM5r > , UsesCL; // R32 >>= cl
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def SHR8rCL : I <"shr", 0xD2, MRM5r > , UsesCL, // R8 >>= cl
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II<(ops R8:$dst, R8:$src), "shr $dst, CL">;
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def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, UsesCL, // R16 >>= cl
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II<(ops R16:$dst, R16:$src), "shr $dst, CL">;
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def SHR32rCL : I <"shr", 0xD3, MRM5r > , UsesCL, // R32 >>= cl
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II<(ops R32:$dst, R32:$src), "shr $dst, CL">;
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def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > , UsesCL; // [mem8] >>= cl
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def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize, UsesCL; // [mem16] >>= cl
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def SHR32mCL : Im32 <"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl
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@ -640,8 +667,10 @@ def TEST32mi : Im32i32<"test", 0xF7, MRM0m >; // flags = [mem32] &
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// Condition code ops, incl. set if equal/not equal/...
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def SAHF : I <"sahf" , 0x9E, RawFrm>, Imp<[AH],[]>; // flags = AH
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def LAHF : I <"lahf" , 0x9F, RawFrm>, Imp<[],[AH]>; // AH = flags
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def SAHF : I <"sahf" , 0x9E, RawFrm>, Imp<[AH],[]>, // flags = AH
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II<(ops), "sahf">;
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def LAHF : I <"lahf" , 0x9F, RawFrm>, Imp<[],[AH]>, // AH = flags
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II<(ops), "lahf">;
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def SETBr : I <"setb" , 0x92, MRM0r>, TB; // R8 = < unsign
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def SETBm : Im8<"setb" , 0x92, MRM0m>, TB; // [mem8] = < unsign
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@ -810,13 +839,17 @@ def FISTP64m : FPI64m <"fistpll", 0xDF, MRM7m , OneArgFP>; // store sig
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def FXCH : FPI <"fxch", 0xC8, AddRegFrm, NotFP>, D9; // fxch ST(i), ST(0)
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// Floating point constant loads...
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def FLD0 : FPI<"fldz", 0xEE, RawFrm, ZeroArgFP>, D9;
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def FLD1 : FPI<"fld1", 0xE8, RawFrm, ZeroArgFP>, D9;
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def FLD0 : FPI<"fldz", 0xEE, RawFrm, ZeroArgFP>, D9,
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II<(ops), "fldz">;
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def FLD1 : FPI<"fld1", 0xE8, RawFrm, ZeroArgFP>, D9,
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II<(ops), "fld1">;
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// Unary operations...
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def FCHS : FPI<"fchs", 0xE0, RawFrm, OneArgFPRW>, D9; // f1 = fchs f2
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def FTST : FPI<"ftst", 0xE4, RawFrm, OneArgFP>, D9; // ftst ST(0)
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def FCHS : FPI<"fchs", 0xE0, RawFrm, OneArgFPRW>, D9, // f1 = fchs f2
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II<(ops), "fchs">;
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def FTST : FPI<"ftst", 0xE4, RawFrm, OneArgFP>, D9, // ftst ST(0)
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II<(ops), "ftst">;
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// Binary arithmetic operations...
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class FPST0rInst<string n, bits<8> o> : I<n, o, AddRegFrm>, D8 {
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@ -858,7 +891,9 @@ def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop
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// Floating point compares
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def FUCOMr : FPI<"fucom", 0xE0, AddRegFrm, CompareFP>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
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def FUCOMPr : I<"fucomp" , 0xE8, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
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def FUCOMPPr : I<"fucompp", 0xE9, RawFrm >, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
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def FUCOMPPr : I<"fucompp", 0xE9, RawFrm >, DA, Imp<[ST0],[]>, // compare ST(0) with ST(1), pop, pop
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II<(ops), "fucompp">;
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let printImplicitUsesBefore = 1 in {
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def FUCOMIr : FPI<"fucomi", 0xE8, AddRegFrm, CompareFP>, DB, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i)
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@ -866,6 +901,8 @@ let printImplicitUsesBefore = 1 in {
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}
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// Floating point flag ops
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def FNSTSW8r : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>; // AX = fp flags
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def FNSTSW8r : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>, // AX = fp flags
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II<(ops), "fnstsw">;
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def FNSTCW16m : Im16<"fnstcw" , 0xD9, MRM7m >; // [mem16] = X87 control world
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def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m >; // X87 control world = [mem16]
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