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Fix gcc -Wsign-compare warning in X86DisassemblerTables.cpp. 

X86_MAX_OPERANDS is changed to unsigned.

Also, add range-based for loops for affected loops. This in turn
needed an ArrayRef instead of a pointer-to-array in
InternalInstruction.

llvm-svn: 207413
This commit is contained in:
Patrik Hagglund 2014-04-28 12:12:27 +00:00
parent 7b839f833d
commit 319983810a
4 changed files with 15 additions and 17 deletions
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8
llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
View File

@ -787,13 +787,11 @@ static bool translateInstruction(MCInst &mcInst,
mcInst.setOpcode(X86::XACQUIRE_PREFIX); mcInst.setOpcode(X86::XACQUIRE_PREFIX);
} }
int index;
insn.numImmediatesTranslated = 0; insn.numImmediatesTranslated = 0;
for (index = 0; index < X86_MAX_OPERANDS; ++index) { for (const auto &Op : insn.operands) {
if (insn.operands[index].encoding != ENCODING_NONE) { if (Op.encoding != ENCODING_NONE) {
if (translateOperand(mcInst, insn.operands[index], insn, Dis)) { if (translateOperand(mcInst, Op, insn, Dis)) {
return true; return true;
} }
} }

19
llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
View File

@ -1663,7 +1663,6 @@ static int readMaskRegister(struct InternalInstruction* insn) {
* @return - 0 if all operands could be read; nonzero otherwise. * @return - 0 if all operands could be read; nonzero otherwise.
*/ */
static int readOperands(struct InternalInstruction* insn) { static int readOperands(struct InternalInstruction* insn) {
int index;
int hasVVVV, needVVVV; int hasVVVV, needVVVV;
int sawRegImm = 0; int sawRegImm = 0;
@ -1674,8 +1673,8 @@ static int readOperands(struct InternalInstruction* insn) {
hasVVVV = !readVVVV(insn); hasVVVV = !readVVVV(insn);
needVVVV = hasVVVV && (insn->vvvv != 0); needVVVV = hasVVVV && (insn->vvvv != 0);
for (index = 0; index < X86_MAX_OPERANDS; ++index) { for (const auto &Op : x86OperandSets[insn->spec->operands]) {
switch (x86OperandSets[insn->spec->operands][index].encoding) { switch (Op.encoding) {
case ENCODING_NONE: case ENCODING_NONE:
case ENCODING_SI: case ENCODING_SI:
case ENCODING_DI: case ENCODING_DI:
@ -1684,7 +1683,7 @@ static int readOperands(struct InternalInstruction* insn) {
case ENCODING_RM: case ENCODING_RM:
if (readModRM(insn)) if (readModRM(insn))
return -1; return -1;
if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index])) if (fixupReg(insn, &Op))
return -1; return -1;
break; break;
case ENCODING_CB: case ENCODING_CB:
@ -1706,14 +1705,14 @@ static int readOperands(struct InternalInstruction* insn) {
} }
if (readImmediate(insn, 1)) if (readImmediate(insn, 1))
return -1; return -1;
if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM3 && if (Op.type == TYPE_IMM3 &&
insn->immediates[insn->numImmediatesConsumed - 1] > 7) insn->immediates[insn->numImmediatesConsumed - 1] > 7)
return -1; return -1;
if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM5 && if (Op.type == TYPE_IMM5 &&
insn->immediates[insn->numImmediatesConsumed - 1] > 31) insn->immediates[insn->numImmediatesConsumed - 1] > 31)
return -1; return -1;
if (x86OperandSets[insn->spec->operands][index].type == TYPE_XMM128 || if (Op.type == TYPE_XMM128 ||
x86OperandSets[insn->spec->operands][index].type == TYPE_XMM256) Op.type == TYPE_XMM256)
sawRegImm = 1; sawRegImm = 1;
break; break;
case ENCODING_IW: case ENCODING_IW:
@ -1762,7 +1761,7 @@ static int readOperands(struct InternalInstruction* insn) {
needVVVV = 0; /* Mark that we have found a VVVV operand. */ needVVVV = 0; /* Mark that we have found a VVVV operand. */
if (!hasVVVV) if (!hasVVVV)
return -1; return -1;
if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index])) if (fixupReg(insn, &Op))
return -1; return -1;
break; break;
case ENCODING_WRITEMASK: case ENCODING_WRITEMASK:
@ -1825,7 +1824,7 @@ int llvm::X86Disassembler::decodeInstruction(
readOperands(insn)) readOperands(insn))
return -1; return -1;
insn->operands = &x86OperandSets[insn->spec->operands][0]; insn->operands = x86OperandSets[insn->spec->operands];
insn->length = insn->readerCursor - insn->startLocation; insn->length = insn->readerCursor - insn->startLocation;

3
llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
View File

@ -17,6 +17,7 @@
#define X86DISASSEMBLERDECODER_H #define X86DISASSEMBLERDECODER_H
#include "X86DisassemblerDecoderCommon.h" #include "X86DisassemblerDecoderCommon.h"
#include "llvm/ADT/ArrayRef.h"
namespace llvm { namespace llvm {
namespace X86Disassembler { namespace X86Disassembler {
@ -620,7 +621,7 @@ struct InternalInstruction {
uint8_t sibScale; uint8_t sibScale;
SIBBase sibBase; SIBBase sibBase;
const OperandSpecifier *operands; ArrayRef<OperandSpecifier> operands;
}; };
/// \brief Decode one instruction and store the decoding results in /// \brief Decode one instruction and store the decoding results in

2
llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
View File

@ -481,7 +481,7 @@ enum ModifierType {
}; };
#undef ENUM_ENTRY #undef ENUM_ENTRY
static const int X86_MAX_OPERANDS = 5; static const unsigned X86_MAX_OPERANDS = 5;
/// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode /// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
/// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, /// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,