[AArch64][SVE] Asm: Add support for SVE INDEX instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro Reviewed By: rengolin, fhahn Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45370 llvm-svn: 329674
This commit is contained in:
Sander de Smalen
parent
0ca3bd0729
commit
30fda45c18
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@ -247,6 +247,17 @@ def simm6_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -32 && Imm < 32; }]>
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let DecoderMethod = "DecodeSImm<6>";
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}
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def SImm5Operand : SImmOperand<5>;
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def simm5_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -16 && Imm < 16; }]> {
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let ParserMatchClass = SImm5Operand;
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let DecoderMethod = "DecodeSImm<5>";
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}
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def simm5_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -16 && Imm < 16; }]> {
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let ParserMatchClass = SImm5Operand;
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let DecoderMethod = "DecodeSImm<5>";
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}
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// simm7sN predicate - True if the immediate is a multiple of N in the range
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// [-64 * N, 63 * N].
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class SImm7Scaled<int Scale> : AsmOperandClass {
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@ -31,4 +31,9 @@ let Predicates = [HasSVE] in {
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def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">;
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def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">;
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def ADDPL_XXI : sve_int_arith_vl<0b1, "addpl">;
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defm INDEX_RR : sve_int_index_rr<"index">;
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defm INDEX_IR : sve_int_index_ir<"index">;
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defm INDEX_RI : sve_int_index_ri<"index">;
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defm INDEX_II : sve_int_index_ii<"index">;
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}
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@ -3537,6 +3537,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
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"expected compatible register or floating-point constant");
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case Match_InvalidMemoryIndexedSImm6:
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return Error(Loc, "index must be an integer in range [-32, 31].");
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case Match_InvalidMemoryIndexedSImm5:
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return Error(Loc, "index must be an integer in range [-16, 15].");
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case Match_InvalidMemoryIndexedSImm9:
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return Error(Loc, "index must be an integer in range [-256, 255].");
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case Match_InvalidMemoryIndexedSImm10:
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@ -4055,6 +4057,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_InvalidMemoryIndexed4SImm7:
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case Match_InvalidMemoryIndexed8SImm7:
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case Match_InvalidMemoryIndexed16SImm7:
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case Match_InvalidMemoryIndexedSImm5:
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case Match_InvalidMemoryIndexedSImm9:
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case Match_InvalidMemoryIndexedSImm10:
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case Match_InvalidImm0_1:
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@ -338,6 +338,107 @@ multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> {
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def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>;
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}
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//===----------------------------------------------------------------------===//
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//SVE Index Generation Group
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//===----------------------------------------------------------------------===//
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class sve_int_index_ii<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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Operand imm_ty>
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: I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b),
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asm, "\t$Zd, $imm5, $imm5b",
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"", []>, Sched<[]> {
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bits<5> Zd;
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bits<5> imm5;
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bits<5> imm5b;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = imm5b;
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let Inst{15-10} = 0b010000;
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let Inst{9-5} = imm5;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_index_ii<string asm> {
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def _B : sve_int_index_ii<0b00, asm, ZPR8, simm5_32b>;
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def _H : sve_int_index_ii<0b01, asm, ZPR16, simm5_32b>;
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def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>;
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def _D : sve_int_index_ii<0b11, asm, ZPR64, simm5_64b>;
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}
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class sve_int_index_ir<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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RegisterClass srcRegType, Operand imm_ty>
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: I<(outs zprty:$Zd), (ins imm_ty:$imm5, srcRegType:$Rm),
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asm, "\t$Zd, $imm5, $Rm",
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"", []>, Sched<[]> {
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bits<5> Rm;
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bits<5> Zd;
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bits<5> imm5;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = Rm;
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let Inst{15-10} = 0b010010;
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let Inst{9-5} = imm5;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_index_ir<string asm> {
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def _B : sve_int_index_ir<0b00, asm, ZPR8, GPR32, simm5_32b>;
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def _H : sve_int_index_ir<0b01, asm, ZPR16, GPR32, simm5_32b>;
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def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>;
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def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>;
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}
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class sve_int_index_ri<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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RegisterClass srcRegType, Operand imm_ty>
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: I<(outs zprty:$Zd), (ins srcRegType:$Rn, imm_ty:$imm5),
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asm, "\t$Zd, $Rn, $imm5",
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"", []>, Sched<[]> {
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bits<5> Rn;
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bits<5> Zd;
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bits<5> imm5;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = imm5;
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let Inst{15-10} = 0b010001;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_index_ri<string asm> {
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def _B : sve_int_index_ri<0b00, asm, ZPR8, GPR32, simm5_32b>;
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def _H : sve_int_index_ri<0b01, asm, ZPR16, GPR32, simm5_32b>;
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def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>;
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def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>;
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}
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class sve_int_index_rr<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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RegisterClass srcRegType>
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: I<(outs zprty:$Zd), (ins srcRegType:$Rn, srcRegType:$Rm),
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asm, "\t$Zd, $Rn, $Rm",
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"", []>, Sched<[]> {
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bits<5> Zd;
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bits<5> Rm;
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bits<5> Rn;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = Rm;
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let Inst{15-10} = 0b010011;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_index_rr<string asm> {
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def _B : sve_int_index_rr<0b00, asm, ZPR8, GPR32>;
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def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>;
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def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;
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def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Permute - Predicates Group
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//===----------------------------------------------------------------------===//
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@ -0,0 +1,58 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-16, 15].
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index z27.b, #-17, #-16
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
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// CHECK-NEXT: index z27.b, #-17, #-16
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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index z11.h, #-16, #-17
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
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// CHECK-NEXT: index z11.h, #-16, #-17
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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index z2.s, #16, #-16
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
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// CHECK-NEXT: index z2.s, #16, #-16
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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index z2.d, #-16, #16
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
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// CHECK-NEXT: index z2.d, #-16, #16
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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index z4.b, #-17, w28
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
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// CHECK-NEXT: index z4.b, #-17, w28
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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index z9.h, #16, w23
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
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// CHECK-NEXT: index z9.h, #16, w23
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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index z3.s, w10, #-17
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
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// CHECK-NEXT: index z3.s, w10, #-17
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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index z17.d, x9, #16
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
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// CHECK-NEXT: index z17.d, x9, #16
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid register
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index z17.s, x9, w7
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
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// CHECK-NEXT: index z17.s, x9, w7
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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index z17.d, w9, w7
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
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// CHECK-NEXT: index z17.d, w9, w7
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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@ -0,0 +1,214 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// --------------------------------------------------------------------------//
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// Index (immediate, immediate)
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index z0.b, #0, #0
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// CHECK-INST: index z0.b, #0, #0
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// CHECK-ENCODING: [0x00,0x40,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 40 20 04 <unknown>
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index z31.b, #-1, #-1
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// CHECK-INST: index z31.b, #-1, #-1
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// CHECK-ENCODING: [0xff,0x43,0x3f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 43 3f 04 <unknown>
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index z0.h, #0, #0
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// CHECK-INST: index z0.h, #0, #0
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// CHECK-ENCODING: [0x00,0x40,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 40 60 04 <unknown>
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index z31.h, #-1, #-1
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// CHECK-INST: index z31.h, #-1, #-1
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// CHECK-ENCODING: [0xff,0x43,0x7f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 43 7f 04 <unknown>
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index z0.s, #0, #0
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// CHECK-INST: index z0.s, #0, #0
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// CHECK-ENCODING: [0x00,0x40,0xa0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 40 a0 04 <unknown>
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index z31.s, #-1, #-1
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// CHECK-INST: index z31.s, #-1, #-1
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// CHECK-ENCODING: [0xff,0x43,0xbf,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 43 bf 04 <unknown>
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index z0.d, #0, #0
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// CHECK-INST: index z0.d, #0, #0
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// CHECK-ENCODING: [0x00,0x40,0xe0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 40 e0 04 <unknown>
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index z31.d, #-1, #-1
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// CHECK-INST: index z31.d, #-1, #-1
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// CHECK-ENCODING: [0xff,0x43,0xff,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 43 ff 04 <unknown>
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// --------------------------------------------------------------------------//
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// Index (immediate, scalar)
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index z31.b, #-1, wzr
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// CHECK-INST: index z31.b, #-1, wzr
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// CHECK-ENCODING: [0xff,0x4b,0x3f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 4b 3f 04 <unknown>
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index z23.b, #13, w8
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// CHECK-INST: index z23.b, #13, w8
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// CHECK-ENCODING: [0xb7,0x49,0x28,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: b7 49 28 04 <unknown>
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index z31.h, #-1, wzr
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// CHECK-INST: index z31.h, #-1, wzr
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// CHECK-ENCODING: [0xff,0x4b,0x7f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 4b 7f 04 <unknown>
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index z23.h, #13, w8
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// CHECK-INST: index z23.h, #13, w8
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// CHECK-ENCODING: [0xb7,0x49,0x68,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: b7 49 68 04 <unknown>
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index z31.s, #-1, wzr
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// CHECK-INST: index z31.s, #-1, wzr
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// CHECK-ENCODING: [0xff,0x4b,0xbf,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 4b bf 04 <unknown>
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index z23.s, #13, w8
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// CHECK-INST: index z23.s, #13, w8
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// CHECK-ENCODING: [0xb7,0x49,0xa8,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: b7 49 a8 04 <unknown>
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index z31.d, #-1, xzr
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// CHECK-INST: index z31.d, #-1, xzr
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// CHECK-ENCODING: [0xff,0x4b,0xff,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 4b ff 04 <unknown>
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index z23.d, #13, x8
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// CHECK-INST: index z23.d, #13, x8
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// CHECK-ENCODING: [0xb7,0x49,0xe8,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: b7 49 e8 04 <unknown>
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// --------------------------------------------------------------------------//
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// Index (scalar, immediate)
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index z31.b, wzr, #-1
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// CHECK-INST: index z31.b, wzr, #-1
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// CHECK-ENCODING: [0xff,0x47,0x3f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 47 3f 04 <unknown>
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index z23.b, w13, #8
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// CHECK-INST: index z23.b, w13, #8
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// CHECK-ENCODING: [0xb7,0x45,0x28,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: b7 45 28 04 <unknown>
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index z31.h, wzr, #-1
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// CHECK-INST: index z31.h, wzr, #-1
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// CHECK-ENCODING: [0xff,0x47,0x7f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 47 7f 04 <unknown>
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index z23.h, w13, #8
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// CHECK-INST: index z23.h, w13, #8
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// CHECK-ENCODING: [0xb7,0x45,0x68,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: b7 45 68 04 <unknown>
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index z31.s, wzr, #-1
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// CHECK-INST: index z31.s, wzr, #-1
|
||||
// CHECK-ENCODING: [0xff,0x47,0xbf,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff 47 bf 04 <unknown>
|
||||
|
||||
index z23.s, w13, #8
|
||||
// CHECK-INST: index z23.s, w13, #8
|
||||
// CHECK-ENCODING: [0xb7,0x45,0xa8,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: b7 45 a8 04 <unknown>
|
||||
|
||||
index z31.d, xzr, #-1
|
||||
// CHECK-INST: index z31.d, xzr, #-1
|
||||
// CHECK-ENCODING: [0xff,0x47,0xff,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff 47 ff 04 <unknown>
|
||||
|
||||
index z23.d, x13, #8
|
||||
// CHECK-INST: index z23.d, x13, #8
|
||||
// CHECK-ENCODING: [0xb7,0x45,0xe8,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: b7 45 e8 04 <unknown>
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Index (scalar, scalar)
|
||||
|
||||
index z31.b, wzr, wzr
|
||||
// CHECK-INST: index z31.b, wzr, wzr
|
||||
// CHECK-ENCODING: [0xff,0x4f,0x3f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff 4f 3f 04 <unknown>
|
||||
|
||||
index z21.b, w10, w21
|
||||
// CHECK-INST: index z21.b, w10, w21
|
||||
// CHECK-ENCODING: [0x55,0x4d,0x35,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 55 4d 35 04 <unknown>
|
||||
|
||||
index z31.h, wzr, wzr
|
||||
// check-inst: index z31.h, wzr, wzr
|
||||
// check-encoding: [0xff,0x4f,0x7f,0x04]
|
||||
// check-error: instruction requires: sve
|
||||
// check-unknown: ff 4f 7f 04 <unknown>
|
||||
|
||||
index z0.h, w0, w0
|
||||
// check-inst: index z0.h, w0, w0
|
||||
// check-encoding: [0x00,0x4c,0x60,0x04]
|
||||
// check-error: instruction requires: sve
|
||||
// check-unknown: 00 4c 60 04 <unknown>
|
||||
|
||||
index z31.s, wzr, wzr
|
||||
// CHECK-INST: index z31.s, wzr, wzr
|
||||
// CHECK-ENCODING: [0xff,0x4f,0xbf,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff 4f bf 04 <unknown>
|
||||
|
||||
index z21.s, w10, w21
|
||||
// CHECK-INST: index z21.s, w10, w21
|
||||
// CHECK-ENCODING: [0x55,0x4d,0xb5,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 55 4d b5 04 <unknown>
|
||||
|
||||
index z31.d, xzr, xzr
|
||||
// CHECK-INST: index z31.d, xzr, xzr
|
||||
// CHECK-ENCODING: [0xff,0x4f,0xff,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff 4f ff 04 <unknown>
|
||||
|
||||
index z21.d, x10, x21
|
||||
// CHECK-INST: index z21.d, x10, x21
|
||||
// CHECK-ENCODING: [0x55,0x4d,0xf5,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 55 4d f5 04 <unknown>
|
||||
Loading…
Reference in New Issue