Use the correct fixup type for ARM VLDR*
llvm-svn: 120604
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@ -658,7 +658,7 @@ getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
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return getAddrModeSOpValue(MI, OpIdx, 1);
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}
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/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
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/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
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uint32_t ARMMCCodeEmitter::
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getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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@ -676,7 +676,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
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assert(MO.isExpr() && "Unexpected machine operand type!");
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const MCExpr *Expr = MO.getExpr();
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MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
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MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
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Fixups.push_back(MCFixup::Create(0, Expr, Kind));
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++MCNumCPRelocations;
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