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When initializing the PIC global base register on ARM/ELF add pc to fix the address. 

This unbreaks PIC with fast isel on ELF targets (PR16717). The output matches
what GCC and SDag do for PIC but may not cover all of the many flavors of PIC
that exist.

llvm-svn: 188551
This commit is contained in:
Benjamin Kramer 2013-08-16 12:52:08 +00:00
parent 19f66290e4
commit 309206667d
2 changed files with 8 additions and 0 deletions
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4
llvm/lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -130,6 +130,10 @@ namespace {
MIB.addImm(0); MIB.addImm(0);
AddDefaultPred(MIB); AddDefaultPred(MIB);
// Fix the GOT address by adding pc.
BuildMI(FirstMBB, MBBI, DL, TII.get(ARM::tPICADD), GlobalBaseReg)
.addReg(GlobalBaseReg).addImm(ARMPCLabelIndex);
return true; return true;
} }

4
llvm/test/CodeGen/ARM/fast-isel-pic.ll
View File

@ -25,6 +25,8 @@ entry:
; ARMv7: add [[reg2]], pc, [[reg2]] ; ARMv7: add [[reg2]], pc, [[reg2]]
; ARMv7-ELF: LoadGV ; ARMv7-ELF: LoadGV
; ARMv7-ELF: ldr r[[reg2:[0-9]+]], ; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
; ARMv7-ELF: .LPC
; ARMv7-ELF-NEXT: add r[[reg2]], pc
; ARMv7-ELF: ldr r[[reg3:[0-9]+]], ; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]] ; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
%tmp = load i32* @g %tmp = load i32* @g
@ -54,6 +56,8 @@ entry:
; ARMv7: ldr r[[reg5]], [r[[reg5]]] ; ARMv7: ldr r[[reg5]], [r[[reg5]]]
; ARMv7-ELF: LoadIndirectSymbol ; ARMv7-ELF: LoadIndirectSymbol
; ARMv7-ELF: ldr r[[reg5:[0-9]+]], ; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
; ARMv7-ELF: .LPC
; ARMv7-ELF-NEXT: add r[[reg5]], pc
; ARMv7-ELF: ldr r[[reg6:[0-9]+]], ; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]] ; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
%tmp = load i32* @i %tmp = load i32* @i