[AArch64] Adjust the cost model for Exynos M1 and M2
Refine the model of FP loads and stores. llvm-svn: 313555
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@ -88,13 +88,37 @@ def M1WriteBX : SchedWriteVariant<[SchedVar<M1BranchLinkFastPred, [M1WriteA1,
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M1WriteC1]>]>;
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M1WriteC1]>]>;
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def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
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def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
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def M1WriteLA : SchedWriteRes<[M1UnitL,
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M1UnitL]> { let Latency = 5; }
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def M1WriteLB : SchedWriteRes<[M1UnitL]> { let Latency = 6;
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let ResourceCycles = [2]; }
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def M1WriteLC : SchedWriteRes<[M1UnitA,
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M1UnitL]> { let Latency = 5; }
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def M1WriteLD : SchedWriteRes<[M1UnitA,
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M1UnitL,
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M1UnitL]> { let Latency = 5; }
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def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
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def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
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SchedVar<NoSchedPred, [M1WriteA1,
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SchedVar<NoSchedPred, [M1WriteA1,
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M1WriteL5]>]>;
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M1WriteL5]>]>;
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def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
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def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
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def M1WriteS2 : SchedWriteRes<[M1UnitS]> { let Latency = 2; }
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def M1WriteS2 : SchedWriteRes<[M1UnitS]> { let Latency = 2; }
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def M1WriteS4 : SchedWriteRes<[M1UnitS]> { let Latency = 4; }
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def M1WriteS4 : SchedWriteRes<[M1UnitS]> { let Latency = 4; }
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def M1WriteSA : SchedWriteRes<[M1UnitS,
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M1UnitFST,
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M1UnitS,
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M1UnitFST]> { let Latency = 1; }
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def M1WriteSB : SchedWriteRes<[M1UnitS,
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M1UnitFST,
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M1UnitA]> { let Latency = 2; }
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def M1WriteSC : SchedWriteRes<[M1UnitS,
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M1UnitFST,
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M1UnitA]> { let Latency = 1; }
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def M1WriteSD : SchedWriteRes<[M1UnitS,
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M1UnitFST,
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M1UnitS,
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M1UnitFST,
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M1UnitA]> { let Latency = 1; }
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def M1WriteSX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
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def M1WriteSX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
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SchedVar<NoSchedPred, [M1WriteA1,
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SchedVar<NoSchedPred, [M1WriteA1,
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M1WriteS1]>]>;
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M1WriteS1]>]>;
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@ -165,7 +189,8 @@ def : WriteRes<WriteFCopy, [M1UnitS]> { let Latency = 4; }
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def : WriteRes<WriteVLD, [M1UnitL]> { let Latency = 5; }
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def : WriteRes<WriteVLD, [M1UnitL]> { let Latency = 5; }
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// FP store instructions.
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// FP store instructions.
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def : WriteRes<WriteVST, [M1UnitS, M1UnitFST]> { let Latency = 1; }
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def : WriteRes<WriteVST, [M1UnitS,
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M1UnitFST]> { let Latency = 1; }
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// ASIMD FP instructions.
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// ASIMD FP instructions.
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def : WriteRes<WriteV, [M1UnitFADD]> { let Latency = 3; }
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def : WriteRes<WriteV, [M1UnitFADD]> { let Latency = 3; }
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@ -404,32 +429,46 @@ def : InstRW<[M1WriteS4], (instregex "^FMOV[WX][DS](High)?r")>;
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def : InstRW<[M1WriteNEONI], (instregex "^FMOV[DS][WX](High)?r")>;
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def : InstRW<[M1WriteNEONI], (instregex "^FMOV[DS][WX](High)?r")>;
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// FP load instructions.
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// FP load instructions.
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def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>;
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def : InstRW<[WriteVLD], (instregex "^LDUR[BDHSQ]i")>;
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def : InstRW<[WriteVLD,
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def : InstRW<[WriteVLD,
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WriteAdr,
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WriteAdr,
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M1WriteA1], (instregex "^LDP[DS](post|pre)")>;
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ReadAdrBase], (instregex "^LDR[BDHSQ](post|pre)")>;
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def : InstRW<[WriteVLD,
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def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>;
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WriteVLD,
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WriteAdr,
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M1WriteA1], (instregex "^LDPQ(post|pre)")>;
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def : InstRW<[M1WriteLX,
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def : InstRW<[M1WriteLX,
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ReadAdrBase], (instregex "^LDR[BDHS]ro[WX]")>;
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ReadAdrBase], (instregex "^LDR[BDHS]ro[WX]")>;
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def : InstRW<[M1WriteA1,
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def : InstRW<[M1WriteLC,
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M1WriteL5,
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ReadAdrBase], (instregex "^LDRQro[WX]")>;
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ReadAdrBase], (instregex "^LDRQro[WX]")>;
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def : InstRW<[WriteVLD,
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WriteLDHi], (instregex "^LDN?P[DS]i")>;
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def : InstRW<[M1WriteLB,
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WriteLDHi], (instregex "^LDN?PQi")>;
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def : InstRW<[M1WriteLC,
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WriteLDHi,
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WriteAdr,
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ReadAdrBase], (instregex "^LDP[DS](post|pre)")>;
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def : InstRW<[M1WriteLD,
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WriteLDHi,
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WriteAdr,
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ReadAdrBase], (instregex "^LDPQ(post|pre)")>;
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// FP store instructions.
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// FP store instructions.
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def : InstRW<[WriteVST], (instregex "^STUR[BDHSQ]i")>;
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def : InstRW<[WriteVST,
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def : InstRW<[WriteVST,
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WriteAdr,
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WriteAdr,
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M1WriteA1], (instregex "^STP[DS](post|pre)")>;
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ReadAdrBase], (instregex "^STR[BDHSQ](post|pre)")>;
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def : InstRW<[WriteVST,
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def : InstRW<[WriteVST], (instregex "^STR[BDHSQ]ui")>;
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WriteVST,
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WriteAdr,
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M1WriteA1], (instregex "^STPQ(post|pre)")>;
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def : InstRW<[M1WriteSY,
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def : InstRW<[M1WriteSY,
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ReadAdrBase], (instregex "^STR[BDHS]ro[WX]")>;
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ReadAdrBase], (instregex "^STR[BDHS]ro[WX]")>;
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def : InstRW<[M1WriteA1,
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def : InstRW<[M1WriteSB,
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M1WriteS2,
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ReadAdrBase], (instregex "^STRQro[WX]")>;
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ReadAdrBase], (instregex "^STRQro[WX]")>;
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def : InstRW<[WriteVST], (instregex "^STN?P[DSQ]i")>;
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def : InstRW<[M1WriteSC,
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WriteAdr,
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ReadAdrBase], (instregex "^STP[DS](post|pre)")>;
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def : InstRW<[M1WriteSD,
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WriteAdr,
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ReadAdrBase], (instregex "^STPQ(post|pre)")>;
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// ASIMD instructions.
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// ASIMD instructions.
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def : InstRW<[M1WriteNMISC3], (instregex "^[SU]ABAL?v")>;
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def : InstRW<[M1WriteNMISC3], (instregex "^[SU]ABAL?v")>;
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