[PowerPC] Materialize i64 constants using rotation with masking
r225135 added the ability to materialize i64 constants using rotations in order to reduce the instruction count. Sometimes we can use a rotation only with some extra masking, so that we take advantage of the fact that generating a bunch of extra higher-order 1 bits is easy using li/lis. llvm-svn: 225147
This commit is contained in:
Hal Finkel
parent
cd17f8fc68
commit
2f61879ff4
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@ -608,9 +608,23 @@ static uint64_t Rot64(uint64_t Imm, unsigned R) {
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static unsigned SelectInt64Count(int64_t Imm) {
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unsigned Count = SelectInt64CountDirect(Imm);
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if (Count == 1)
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return Count;
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for (unsigned r = 1; r < 63; ++r) {
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unsigned RCount = SelectInt64CountDirect(Rot64(Imm, r)) + 1;
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uint64_t RImm = Rot64(Imm, r);
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unsigned RCount = SelectInt64CountDirect(RImm) + 1;
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Count = std::min(Count, RCount);
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// See comments in SelectInt64 for an explanation of the logic below.
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unsigned LS = findLastSet(RImm);
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if (LS != r-1)
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continue;
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uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
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uint64_t RImmWithOnes = RImm | OnesMask;
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RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
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Count = std::min(Count, RCount);
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}
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@ -695,13 +709,45 @@ static SDNode *SelectInt64Direct(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
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static SDNode *SelectInt64(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
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unsigned Count = SelectInt64CountDirect(Imm);
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if (Count == 1)
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return SelectInt64Direct(CurDAG, dl, Imm);
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unsigned RMin = 0;
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int64_t MatImm;
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unsigned MaskEnd;
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for (unsigned r = 1; r < 63; ++r) {
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unsigned RCount = SelectInt64CountDirect(Rot64(Imm, r)) + 1;
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uint64_t RImm = Rot64(Imm, r);
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unsigned RCount = SelectInt64CountDirect(RImm) + 1;
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if (RCount < Count) {
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Count = RCount;
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RMin = r;
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MatImm = RImm;
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MaskEnd = 63;
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}
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// If the immediate to generate has many trailing zeros, it might be
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// worthwhile to generate a rotated value with too many leading ones
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// (because that's free with li/lis's sign-extension semantics), and then
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// mask them off after rotation.
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unsigned LS = findLastSet(RImm);
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// We're adding (63-LS) higher-order ones, and we expect to mask them off
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// after performing the inverse rotation by (64-r). So we need that:
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// 63-LS == 64-r => LS == r-1
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if (LS != r-1)
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continue;
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uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
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uint64_t RImmWithOnes = RImm | OnesMask;
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RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
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if (RCount < Count) {
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Count = RCount;
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RMin = r;
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MatImm = RImmWithOnes;
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MaskEnd = LS;
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}
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}
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@ -712,9 +758,9 @@ static SDNode *SelectInt64(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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};
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SDValue Val = SDValue(SelectInt64Direct(CurDAG, dl, Rot64(Imm, RMin)), 0);
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return CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Val,
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getI32Imm(64 - RMin), getI32Imm(0));
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SDValue Val = SDValue(SelectInt64Direct(CurDAG, dl, MatImm), 0);
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return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
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getI32Imm(64 - RMin), getI32Imm(MaskEnd));
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}
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// Select a 64-bit constant.
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@ -5,27 +5,6 @@ TODO:
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===-------------------------------------------------------------------------===
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On PPC64, this:
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long f2 (long x) { return 0xfffffff000000000UL; }
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could compile into:
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_f2:
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li r3,-1
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rldicr r3,r3,0,27
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blr
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we produce:
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_f2:
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lis r2, 4095
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ori r2, r2, 65535
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sldi r3, r2, 36
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blr
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===-------------------------------------------------------------------------===
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This code:
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unsigned add32carry(unsigned sum, unsigned x) {
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@ -9,7 +9,7 @@ entry:
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; CHECK-LABEL: @cn1
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; CHECK: lis [[REG1:[0-9]+]], -1
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; CHECK: rldicl 3, [[REG1]], 48, 0
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; CHECK: rldicr 3, [[REG1]], 48, 63
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; CHECK: blr
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}
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@ -20,7 +20,29 @@ entry:
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; CHECK-LABEL: @cnb
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; CHECK: lis [[REG1:[0-9]+]], -81
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; CHECK: rldicl 3, [[REG1]], 48, 0
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; CHECK: rldicr 3, [[REG1]], 48, 63
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define i64 @f2(i64 %x) #0 {
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entry:
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ret i64 -68719476736
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; CHECK-LABEL: @f2
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; CHECK: li [[REG1:[0-9]+]], -1
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; CHECK: sldi 3, [[REG1]], 36
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define i64 @f2a(i64 %x) #0 {
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entry:
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ret i64 -361850994688
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; CHECK-LABEL: @f2a
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; CHECK: li [[REG1:[0-9]+]], -337
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; CHECK: sldi 3, [[REG1]], 30
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; CHECK: blr
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}
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@ -31,7 +53,7 @@ entry:
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; CHECK-LABEL: @f2n
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; CHECK: lis [[REG1:[0-9]+]], -4096
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; CHECK: rldicl 3, [[REG1]], 36, 0
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; CHECK: rldicr 3, [[REG1]], 36, 63
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; CHECK: blr
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}
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@ -42,7 +64,7 @@ entry:
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; CHECK-LABEL: @f3
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; CHECK: lis [[REG1:[0-9]+]], -32768
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; CHECK: rldicl 3, [[REG1]], 33, 0
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; CHECK: rldicr 3, [[REG1]], 33, 63
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; CHECK: blr
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}
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@ -54,11 +76,9 @@ entry:
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; CHECK-LABEL: @cn2n
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; CHECK: lis [[REG1:[0-9]+]], -5121
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; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 65534
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; CHECK: rldicl 3, [[REG2]], 22, 0
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; CHECK: rldicr 3, [[REG2]], 22, 63
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; CHECK: blr
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}
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attributes #0 = { nounwind readnone }
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