[arm fast-isel] Appease the machine verifier by using the proper register
classes. Also a bit of cleanup. rdar://12719844 llvm-svn: 168728
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@ -1667,7 +1667,6 @@ bool ARMFastISel::SelectSelect(const Instruction *I) {
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// Things need to be register sized for register moves.
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if (VT != MVT::i32) return false;
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const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
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unsigned CondReg = getRegForValue(I->getOperand(0));
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if (CondReg == 0) return false;
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@ -1700,14 +1699,16 @@ bool ARMFastISel::SelectSelect(const Instruction *I) {
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.addReg(CondReg).addImm(0));
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unsigned MovCCOpc;
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const TargetRegisterClass *RC;
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if (!UseImm) {
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RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
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MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
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} else {
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if (!isNegativeImm) {
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RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
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if (!isNegativeImm)
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MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
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} else {
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else
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MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
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}
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}
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unsigned ResultReg = createResultReg(RC);
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if (!UseImm)
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@ -2589,7 +2590,7 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
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Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
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} else {
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Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
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RC = isThumb2 ?&ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
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RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
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}
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break;
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case MVT::i8:
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