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[mips] Add support for -mfpxx and -mno-fpxx. 

Differential Revision: http://reviews.llvm.org/D4464

llvm-svn: 213132
This commit is contained in:
Daniel Sanders 2014-07-16 09:57:54 +00:00
parent 39c28e86a6
commit 2e9427a175
3 changed files with 19 additions and 0 deletions
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3
clang/include/clang/Driver/Options.td
View File

@ -1261,6 +1261,9 @@ def mips64r2 : Flag<["-"], "mips64r2">,
def mips64r6 : Flag<["-"], "mips64r6">,
Alias<march_EQ>, AliasArgs<["mips64r6"]>,
HelpText<"Equivalent to -march=mips64r6">, Flags<[HelpHidden]>;
def mfpxx : Flag<["-"], "mfpxx">, Group<m_Group>,
HelpText<"Avoid FPU mode dependent operations when used with the O32 ABI">,
Flags<[HelpHidden]>;
def modd_spreg : Flag<["-"], "modd-spreg">, Group<m_Group>,
HelpText<"Enable odd single-precision floating point registers">,
Flags<[HelpHidden]>;

4
clang/lib/Driver/Tools.cpp
View File

@ -1058,6 +1058,10 @@ static void getMIPSTargetFeatures(const Driver &D, const ArgList &Args,
"msa");
AddTargetFeature(Args, Features, options::OPT_mfp64, options::OPT_mfp32,
"fp64");
if (Args.getLastArg(options::OPT_mfpxx)) {
Features.push_back(Args.MakeArgString("+fpxx"));
Features.push_back(Args.MakeArgString("+nooddspreg"));
}
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
options::OPT_modd_spreg, "nooddspreg");
}

12
clang/test/Driver/mips-features.c
View File

@ -70,6 +70,18 @@
// RUN: | FileCheck --check-prefix=CHECK-NOMODDSPREG %s
// CHECK-NOMODDSPREG: "-target-feature" "+nooddspreg"
//
// -mfpxx
// RUN: %clang -target mips-linux-gnu -### -c %s -mfpxx 2>&1 \
// RUN: | FileCheck --check-prefix=CHECK-MFPXX %s
// CHECK-MFPXX: "-target-feature" "+fpxx"
// CHECK-MFPXX: "-target-feature" "+nooddspreg"
//
// -mfpxx -modd-spreg
// RUN: %clang -target mips-linux-gnu -### -c %s -mfpxx -modd-spreg 2>&1 \
// RUN: | FileCheck --check-prefix=CHECK-MFPXX-ODDSPREG %s
// CHECK-MFPXX-ODDSPREG: "-target-feature" "+fpxx"
// CHECK-MFPXX-ODDSPREG: "-target-feature" "-nooddspreg"
//
// -mfp64
// RUN: %clang -target mips-linux-gnu -### -c %s \
// RUN: -mfp32 -mfp64 2>&1 \