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Fixes to read the floating point and exception registers sets out 

of arm Mach-O core files.
<rdar://problem/13665075>

llvm-svn: 181755
This commit is contained in:
Jason Molenda 2013-05-14 03:25:58 +00:00
parent cad47f0297
commit 2e7236fa66
2 changed files with 47 additions and 23 deletions
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54
lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
View File

@ -289,25 +289,43 @@ public:
SetError (GPRRegSet, Read, -1); SetError (GPRRegSet, Read, -1);
SetError (FPURegSet, Read, -1); SetError (FPURegSet, Read, -1);
SetError (EXCRegSet, Read, -1); SetError (EXCRegSet, Read, -1);
int flavor = data.GetU32 (&offset); bool done = false;
uint32_t count = data.GetU32 (&offset);
switch (flavor) while (!done)
{ {
case GPRRegSet: int flavor = data.GetU32 (&offset);
for (uint32_t i=0; i<count; ++i) uint32_t count = data.GetU32 (&offset);
gpr.r[i] = data.GetU32(&offset); switch (flavor)
SetError (GPRRegSet, Read, 0); {
break; case GPRRegSet:
case FPURegSet: for (uint32_t i=0; i<count; ++i)
// TODO: fill in FPU regs.... gpr.r[i] = data.GetU32(&offset);
//SetError (FPURegSet, Read, -1); SetError (GPRRegSet, Read, 0);
break; break;
case EXCRegSet:
exc.exception = data.GetU32(&offset); case FPURegSet:
exc.fsr = data.GetU32(&offset); {
exc.far = data.GetU32(&offset); uint32_t *d = &fpu.floats.s[0];
SetError (EXCRegSet, Read, 0); for (uint32_t i = 0; i < count && d < d + (sizeof (fpu.floats) / sizeof (uint32_t)); i++)
break; {
*d++ = data.GetU32(&offset);
}
SetError (FPURegSet, Read, 0);
}
break;
case EXCRegSet:
exc.exception = data.GetU32(&offset);
exc.fsr = data.GetU32(&offset);
exc.far = data.GetU32(&offset);
SetError (EXCRegSet, Read, 0);
done = true;
break;
// Unknown register set flavor, stop trying to parse.
default:
done = true;
}
} }
} }
protected: protected:

16
lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm.h
View File

@ -114,11 +114,17 @@ public:
}; };
struct QReg
{
uint8_t bytes[16];
};
struct FPU struct FPU
{ {
union { union {
uint32_t s[32]; uint32_t s[32];
uint64_t d[16]; uint64_t d[32];
QReg q[16]; // the 128-bit NEON registers
} floats; } floats;
uint32_t fpscr; uint32_t fpscr;
}; };
@ -160,10 +166,10 @@ protected:
enum enum
{ {
GPRRegSet = 1, GPRRegSet = 1, // ARM_THREAD_STATE
FPURegSet = 2, FPURegSet = 2, // ARM_VFP_STATE
EXCRegSet = 3, EXCRegSet = 3, // ARM_EXCEPTION_STATE
DBGRegSet = 4 DBGRegSet = 4 // ARM_DEBUG_STATE
}; };
enum enum