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This patch implements wait instruction for mips. Examples are added in test files. 

llvm-svn: 188537
This commit is contained in:
Vladimir Medic 2013-08-16 10:17:03 +00:00
parent f0a84f200a
commit 2df9ee6ec8
2 changed files with 15 additions and 0 deletions
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11
llvm/lib/Target/Mips/MipsInstrInfo.td
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@ -673,6 +673,15 @@ class DEI_FT<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$rt), (ins),
!strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
// Wait
class WAIT_FT<string opstr> :
InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> {
let Inst{31-26} = 0x10;
let Inst{25} = 1;
let Inst{24-6} = 0;
let Inst{5-0} = 0x20;
}
// Sync
let hasSideEffects = 1 in
class SYNC_FT :
@ -990,6 +999,8 @@ def DERET : ER_FT<"deret">, ER_FM<0x1f>;
def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
def WAIT : WAIT_FT<"wait">;
/// Load-linked, Store-conditional
let Predicates = [NotN64, HasStdEnc] in {
def LL : LLBase<"ll", GPR32Opnd, mem>, LW_FM<0x30>;

4
llvm/test/MC/Mips/mips-control-instructions.s
View File

@ -16,6 +16,7 @@
# CHECK32: ei # encoding: [0x41,0x60,0x60,0x20]
# CHECK32: ei # encoding: [0x41,0x60,0x60,0x20]
# CHECK32: ei $10 # encoding: [0x41,0x6a,0x60,0x20]
# CHECK32: wait # encoding: [0x42,0x00,0x00,0x20]
# CHECK64: break # encoding: [0x00,0x00,0x00,0x0d]
# CHECK64: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d]
@ -30,6 +31,7 @@
# CHECK64: ei # encoding: [0x41,0x60,0x60,0x20]
# CHECK64: ei # encoding: [0x41,0x60,0x60,0x20]
# CHECK64: ei $10 # encoding: [0x41,0x6a,0x60,0x20]
# CHECK64: wait # encoding: [0x42,0x00,0x00,0x20]
break
break 7
break 7,5
@ -44,3 +46,5 @@
ei
ei $0
ei $10
wait