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Move more passes to using ETForest instead of DominatorTree. 

llvm-svn: 36271
This commit is contained in:
Owen Anderson 2007-04-20 06:27:13 +00:00
parent 7a5136d8c5
commit 2da606c757
5 changed files with 19 additions and 23 deletions
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4
llvm/include/llvm/Transforms/Utils/PromoteMemToReg.h
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@ -20,7 +20,7 @@
namespace llvm { namespace llvm {
class AllocaInst; class AllocaInst;
class DominatorTree; class ETForest;
class DominanceFrontier; class DominanceFrontier;
class TargetData; class TargetData;
class AliasSetTracker; class AliasSetTracker;
@ -39,7 +39,7 @@ bool isAllocaPromotable(const AllocaInst *AI, const TargetData &TD);
/// made to the IR. /// made to the IR.
/// ///
void PromoteMemToReg(const std::vector<AllocaInst*> &Allocas, void PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
DominatorTree &DT, DominanceFrontier &DF, ETForest &ET, DominanceFrontier &DF,
const TargetData &TD, AliasSetTracker *AST = 0); const TargetData &TD, AliasSetTracker *AST = 0);
} // End llvm namespace } // End llvm namespace

7
llvm/lib/Transforms/Scalar/LICM.cpp
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@ -73,7 +73,6 @@ namespace {
AU.addRequiredID(LoopSimplifyID); AU.addRequiredID(LoopSimplifyID);
AU.addRequired<LoopInfo>(); AU.addRequired<LoopInfo>();
AU.addRequired<ETForest>(); AU.addRequired<ETForest>();
AU.addRequired<DominatorTree>(); // For scalar promotion (mem2reg)
AU.addRequired<DominanceFrontier>(); // For scalar promotion (mem2reg) AU.addRequired<DominanceFrontier>(); // For scalar promotion (mem2reg)
AU.addRequired<AliasAnalysis>(); AU.addRequired<AliasAnalysis>();
} }
@ -88,7 +87,6 @@ namespace {
AliasAnalysis *AA; // Current AliasAnalysis information AliasAnalysis *AA; // Current AliasAnalysis information
LoopInfo *LI; // Current LoopInfo LoopInfo *LI; // Current LoopInfo
ETForest *ET; // ETForest for the current Loop... ETForest *ET; // ETForest for the current Loop...
DominatorTree *DT; // Dominator Tree for the current Loop...
DominanceFrontier *DF; // Current Dominance Frontier DominanceFrontier *DF; // Current Dominance Frontier
// State that is updated as we process loops // State that is updated as we process loops
@ -215,7 +213,6 @@ bool LICM::runOnLoop(Loop *L, LPPassManager &LPM) {
AA = &getAnalysis<AliasAnalysis>(); AA = &getAnalysis<AliasAnalysis>();
DF = &getAnalysis<DominanceFrontier>(); DF = &getAnalysis<DominanceFrontier>();
ET = &getAnalysis<ETForest>(); ET = &getAnalysis<ETForest>();
DT = &getAnalysis<DominatorTree>();
CurAST = new AliasSetTracker(*AA); CurAST = new AliasSetTracker(*AA);
// Collect Alias info frmo subloops // Collect Alias info frmo subloops
@ -554,7 +551,7 @@ void LICM::sink(Instruction &I) {
if (AI) { if (AI) {
std::vector<AllocaInst*> Allocas; std::vector<AllocaInst*> Allocas;
Allocas.push_back(AI); Allocas.push_back(AI);
PromoteMemToReg(Allocas, *DT, *DF, AA->getTargetData(), CurAST); PromoteMemToReg(Allocas, *ET, *DF, AA->getTargetData(), CurAST);
} }
} }
} }
@ -735,7 +732,7 @@ void LICM::PromoteValuesInLoop() {
PromotedAllocas.reserve(PromotedValues.size()); PromotedAllocas.reserve(PromotedValues.size());
for (unsigned i = 0, e = PromotedValues.size(); i != e; ++i) for (unsigned i = 0, e = PromotedValues.size(); i != e; ++i)
PromotedAllocas.push_back(PromotedValues[i].first); PromotedAllocas.push_back(PromotedValues[i].first);
PromoteMemToReg(PromotedAllocas, *DT, *DF, AA->getTargetData(), CurAST); PromoteMemToReg(PromotedAllocas, *ET, *DF, AA->getTargetData(), CurAST);
} }
/// FindPromotableValuesInLoop - Check the current loop for stores to definite /// FindPromotableValuesInLoop - Check the current loop for stores to definite

6
llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
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@ -53,7 +53,7 @@ namespace {
// getAnalysisUsage - This pass does not require any passes, but we know it // getAnalysisUsage - This pass does not require any passes, but we know it
// will not alter the CFG, so say so. // will not alter the CFG, so say so.
virtual void getAnalysisUsage(AnalysisUsage &AU) const { virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<DominatorTree>(); AU.addRequired<ETForest>();
AU.addRequired<DominanceFrontier>(); AU.addRequired<DominanceFrontier>();
AU.addRequired<TargetData>(); AU.addRequired<TargetData>();
AU.setPreservesCFG(); AU.setPreservesCFG();
@ -100,7 +100,7 @@ bool SROA::runOnFunction(Function &F) {
bool SROA::performPromotion(Function &F) { bool SROA::performPromotion(Function &F) {
std::vector<AllocaInst*> Allocas; std::vector<AllocaInst*> Allocas;
const TargetData &TD = getAnalysis<TargetData>(); const TargetData &TD = getAnalysis<TargetData>();
DominatorTree &DT = getAnalysis<DominatorTree>(); ETForest &ET = getAnalysis<ETForest>();
DominanceFrontier &DF = getAnalysis<DominanceFrontier>(); DominanceFrontier &DF = getAnalysis<DominanceFrontier>();
BasicBlock &BB = F.getEntryBlock(); // Get the entry node for the function BasicBlock &BB = F.getEntryBlock(); // Get the entry node for the function
@ -119,7 +119,7 @@ bool SROA::performPromotion(Function &F) {
if (Allocas.empty()) break; if (Allocas.empty()) break;
PromoteMemToReg(Allocas, DT, DF, TD); PromoteMemToReg(Allocas, ET, DF, TD);
NumPromoted += Allocas.size(); NumPromoted += Allocas.size();
Changed = true; Changed = true;
} }

6
llvm/lib/Transforms/Utils/Mem2Reg.cpp
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@ -36,7 +36,7 @@ namespace {
// getAnalysisUsage - We need dominance frontiers // getAnalysisUsage - We need dominance frontiers
// //
virtual void getAnalysisUsage(AnalysisUsage &AU) const { virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<DominatorTree>(); AU.addRequired<ETForest>();
AU.addRequired<DominanceFrontier>(); AU.addRequired<DominanceFrontier>();
AU.addRequired<TargetData>(); AU.addRequired<TargetData>();
AU.setPreservesCFG(); AU.setPreservesCFG();
@ -60,7 +60,7 @@ bool PromotePass::runOnFunction(Function &F) {
bool Changed = false; bool Changed = false;
DominatorTree &DT = getAnalysis<DominatorTree>(); ETForest &ET = getAnalysis<ETForest>();
DominanceFrontier &DF = getAnalysis<DominanceFrontier>(); DominanceFrontier &DF = getAnalysis<DominanceFrontier>();
while (1) { while (1) {
@ -75,7 +75,7 @@ bool PromotePass::runOnFunction(Function &F) {
if (Allocas.empty()) break; if (Allocas.empty()) break;
PromoteMemToReg(Allocas, DT, DF, TD); PromoteMemToReg(Allocas, ET, DF, TD);
NumPromoted += Allocas.size(); NumPromoted += Allocas.size();
Changed = true; Changed = true;
} }

19
llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
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@ -88,7 +88,7 @@ namespace {
/// ///
std::vector<AllocaInst*> Allocas; std::vector<AllocaInst*> Allocas;
SmallVector<AllocaInst*, 16> &RetryList; SmallVector<AllocaInst*, 16> &RetryList;
DominatorTree &DT; ETForest &ET;
DominanceFrontier &DF; DominanceFrontier &DF;
const TargetData &TD; const TargetData &TD;
@ -127,10 +127,10 @@ namespace {
public: public:
PromoteMem2Reg(const std::vector<AllocaInst*> &A, PromoteMem2Reg(const std::vector<AllocaInst*> &A,
SmallVector<AllocaInst*, 16> &Retry, DominatorTree &dt, SmallVector<AllocaInst*, 16> &Retry, ETForest &et,
DominanceFrontier &df, const TargetData &td, DominanceFrontier &df, const TargetData &td,
AliasSetTracker *ast) AliasSetTracker *ast)
: Allocas(A), RetryList(Retry), DT(dt), DF(df), TD(td), AST(ast) {} : Allocas(A), RetryList(Retry), ET(et), DF(df), TD(td), AST(ast) {}
void run(); void run();
@ -139,13 +139,13 @@ namespace {
bool properlyDominates(Instruction *I1, Instruction *I2) const { bool properlyDominates(Instruction *I1, Instruction *I2) const {
if (InvokeInst *II = dyn_cast<InvokeInst>(I1)) if (InvokeInst *II = dyn_cast<InvokeInst>(I1))
I1 = II->getNormalDest()->begin(); I1 = II->getNormalDest()->begin();
return DT[I1->getParent()]->properlyDominates(DT[I2->getParent()]); return ET.properlyDominates(I1->getParent(), I2->getParent());
} }
/// dominates - Return true if BB1 dominates BB2 using the DominatorTree. /// dominates - Return true if BB1 dominates BB2 using the DominatorTree.
/// ///
bool dominates(BasicBlock *BB1, BasicBlock *BB2) const { bool dominates(BasicBlock *BB1, BasicBlock *BB2) const {
return DT[BB1]->dominates(DT[BB2]); return ET.dominates(BB1, BB2);
} }
private: private:
@ -534,8 +534,7 @@ void PromoteMem2Reg::MarkDominatingPHILive(BasicBlock *BB, unsigned AllocaNum,
SmallPtrSet<PHINode*, 16> &DeadPHINodes) { SmallPtrSet<PHINode*, 16> &DeadPHINodes) {
// Scan the immediate dominators of this block looking for a block which has a // Scan the immediate dominators of this block looking for a block which has a
// PHI node for Alloca num. If we find it, mark the PHI node as being alive! // PHI node for Alloca num. If we find it, mark the PHI node as being alive!
for (DominatorTree::Node *N = DT[BB]; N; N = N->getIDom()) { for (BasicBlock* DomBB = BB; DomBB; DomBB = ET.getIDom(DomBB)) {
BasicBlock *DomBB = N->getBlock();
DenseMap<std::pair<BasicBlock*, unsigned>, PHINode*>::iterator DenseMap<std::pair<BasicBlock*, unsigned>, PHINode*>::iterator
I = NewPhiNodes.find(std::make_pair(DomBB, AllocaNum)); I = NewPhiNodes.find(std::make_pair(DomBB, AllocaNum));
if (I != NewPhiNodes.end()) { if (I != NewPhiNodes.end()) {
@ -806,13 +805,13 @@ void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred,
/// made to the IR. /// made to the IR.
/// ///
void llvm::PromoteMemToReg(const std::vector<AllocaInst*> &Allocas, void llvm::PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
DominatorTree &DT, DominanceFrontier &DF, ETForest &ET, DominanceFrontier &DF,
const TargetData &TD, AliasSetTracker *AST) { const TargetData &TD, AliasSetTracker *AST) {
// If there is nothing to do, bail out... // If there is nothing to do, bail out...
if (Allocas.empty()) return; if (Allocas.empty()) return;
SmallVector<AllocaInst*, 16> RetryList; SmallVector<AllocaInst*, 16> RetryList;
PromoteMem2Reg(Allocas, RetryList, DT, DF, TD, AST).run(); PromoteMem2Reg(Allocas, RetryList, ET, DF, TD, AST).run();
// PromoteMem2Reg may not have been able to promote all of the allocas in one // PromoteMem2Reg may not have been able to promote all of the allocas in one
// pass, run it again if needed. // pass, run it again if needed.
@ -830,7 +829,7 @@ void llvm::PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
NewAllocas.assign(RetryList.begin(), RetryList.end()); NewAllocas.assign(RetryList.begin(), RetryList.end());
RetryList.clear(); RetryList.clear();
PromoteMem2Reg(NewAllocas, RetryList, DT, DF, TD, AST).run(); PromoteMem2Reg(NewAllocas, RetryList, ET, DF, TD, AST).run();
NewAllocas.clear(); NewAllocas.clear();
} }
} }