Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
llvm-svn: 118922
This commit is contained in:
Evan Cheng
parent
6bb1ae9d45
commit
2d59ee34f1
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@ -168,7 +168,8 @@ def : Processor<"cortex-a8", CortexA8Itineraries,
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[ArchV7A, ProcA8,
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FeatureHasSlowVMLx, FeatureT2XtPk]>;
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def : Processor<"cortex-a9", CortexA9Itineraries,
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[ArchV7A, ProcA9, FeatureT2XtPk]>;
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[ArchV7A, ProcA9,
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FeatureHasSlowVMLx, FeatureT2XtPk]>;
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// V7M Processors.
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def : ProcNoItin<"cortex-m3", [ArchV7M]>;
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@ -1577,33 +1577,6 @@ class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
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let Inst{4} = op4;
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}
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// Double precision, binary, VML[AS] (for additional predicate)
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class ADbI_vmlX<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
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dag iops, InstrItinClass itin, string opc, string asm,
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list<dag> pattern>
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: VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
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// Instruction operands.
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bits<5> Dd;
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bits<5> Dn;
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bits<5> Dm;
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// Encode instruction operands.
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let Inst{19-16} = Dn{3-0};
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let Inst{7} = Dn{4};
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let Inst{15-12} = Dd{3-0};
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let Inst{22} = Dd{4};
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let Inst{3-0} = Dm{3-0};
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let Inst{5} = Dm{4};
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let Inst{27-23} = opcod1;
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let Inst{21-20} = opcod2;
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let Inst{11-9} = 0b101;
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let Inst{8} = 1; // Double precision
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let Inst{6} = op6;
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let Inst{4} = op4;
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list<Predicate> Predicates = [HasVFP2, UseVMLx];
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}
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// Single precision, unary
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class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
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bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
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@ -738,80 +738,96 @@ def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
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// FP FMA Operations.
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//
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def VMLAD : ADbI_vmlX<0b11100, 0b00, 0, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
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[(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">;
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def VMLAD : ADbI<0b11100, 0b00, 0, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
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[(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">,
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Requires<[HasVFP2,UseVMLx]>;
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def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fadd (fmul SPR:$Sn, SPR:$Sm),
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">;
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>;
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def : Pat<(fadd DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
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(VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
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(VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
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Requires<[HasVFP2,UseVMLx]>;
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def : Pat<(fadd SPR:$dstin, (fmul SPR:$a, SPR:$b)),
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(VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
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(VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
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Requires<[HasVFP2,DontUseNEONForFP, UseVMLx]>;
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def VMLSD : ADbI_vmlX<0b11100, 0b00, 1, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
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[(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">;
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def VMLSD : ADbI<0b11100, 0b00, 1, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
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[(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">,
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Requires<[HasVFP2,UseVMLx]>;
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def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fadd (fneg (fmul SPR:$Sn, SPR:$Sm)),
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">;
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>;
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def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
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(VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
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(VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
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Requires<[HasVFP2,UseVMLx]>;
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def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
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(VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
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(VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
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Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>;
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def VNMLAD : ADbI_vmlX<0b11100, 0b01, 1, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
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[(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">;
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def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
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[(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">,
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Requires<[HasVFP2,UseVMLx]>;
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def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fsub (fneg (fmul SPR:$Sn, SPR:$Sm)),
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">;
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>;
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def : Pat<(fsub (fneg (fmul DPR:$a, (f64 DPR:$b))), DPR:$dstin),
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(VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
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(VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
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Requires<[HasVFP2,UseVMLx]>;
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def : Pat<(fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin),
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(VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
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(VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
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Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>;
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def VNMLSD : ADbI_vmlX<0b11100, 0b01, 0, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
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[(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">;
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def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
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[(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">,
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Requires<[HasVFP2,UseVMLx]>;
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def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fsub (fmul SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">;
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>;
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def : Pat<(fsub (fmul DPR:$a, (f64 DPR:$b)), DPR:$dstin),
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(VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
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(VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
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Requires<[HasVFP2,UseVMLx]>;
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def : Pat<(fsub (fmul SPR:$a, SPR:$b), SPR:$dstin),
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(VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
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(VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
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Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>;
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//===----------------------------------------------------------------------===//
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@ -1,24 +1,51 @@
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; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
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; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
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define float @test(float %acc, float %a, float %b) {
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define float @t1(float %acc, float %a, float %b) {
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entry:
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; VFP2: t1:
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; VFP2: vmla.f32
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; NEON: t1:
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; NEON: vmla.f32
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; A8: t1:
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; A8: vmul.f32
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; A8: vadd.f32
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%0 = fmul float %a, %b
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%1 = fadd float %acc, %0
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ret float %1
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}
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; VFP2: test:
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; VFP2: vmla.f32 s2, s1, s0
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define double @t2(double %acc, double %a, double %b) {
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entry:
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; VFP2: t2:
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; VFP2: vmla.f64
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; NFP1: test:
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; NFP1: vmul.f32 d0, d1, d0
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; NFP0: test:
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; NFP0: vmla.f32 s2, s1, s0
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; NEON: t2:
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; NEON: vmla.f64
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; CORTEXA8: test:
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; CORTEXA8: vmul.f32 d0, d1, d0
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; CORTEXA9: test:
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; CORTEXA9: vmla.f32 s2, s1, s0
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; A8: t2:
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; A8: vmul.f64
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; A8: vadd.f64
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%0 = fmul double %a, %b
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%1 = fadd double %acc, %0
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ret double %1
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}
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define float @t3(float %acc, float %a, float %b) {
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entry:
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; VFP2: t3:
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; VFP2: vmla.f32
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; NEON: t3:
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; NEON: vmla.f32
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; A8: t3:
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; A8: vmul.f32
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; A8: vadd.f32
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%0 = fmul float %a, %b
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%1 = fadd float %0, %acc
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ret float %1
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}
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@ -1,24 +1,35 @@
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; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
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; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
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define float @test(float %acc, float %a, float %b) {
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define float @t1(float %acc, float %a, float %b) {
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entry:
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; VFP2: t1:
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; VFP2: vnmls.f32
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; NEON: t1:
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; NEON: vnmls.f32
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; A8: t1:
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; A8: vmul.f32
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; A8: vsub.f32
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%0 = fmul float %a, %b
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%1 = fsub float %0, %acc
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ret float %1
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}
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; VFP2: test:
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; VFP2: vnmls.f32 s2, s1, s0
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define double @t2(double %acc, double %a, double %b) {
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entry:
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; VFP2: t2:
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; VFP2: vnmls.f64
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; NFP1: test:
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; NFP1: vnmls.f32 s2, s1, s0
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; NFP0: test:
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; NFP0: vnmls.f32 s2, s1, s0
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; NEON: t2:
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; NEON: vnmls.f64
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; CORTEXA8: test:
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; CORTEXA8: vnmls.f32 s2, s1, s0
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; CORTEXA9: test:
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; CORTEXA9: vnmls.f32 s2, s1, s0
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; A8: t2:
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; A8: vmul.f64
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; A8: vsub.f64
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%0 = fmul double %a, %b
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%1 = fsub double %0, %acc
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ret double %1
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}
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@ -1,20 +1,35 @@
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; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEONFP
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
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define float @test(float %acc, float %a, float %b) {
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define float @t1(float %acc, float %a, float %b) {
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entry:
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; VFP2: t1:
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; VFP2: vmls.f32
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; NEON: t1:
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; NEON: vmls.f32
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; NEONFP-NOT: vmls
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; NEONFP-NOT: vmov.f32
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; NEONFP: vmul.f32
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; NEONFP: vsub.f32
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; NEONFP: vmov
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; A8: t1:
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; A8: vmul.f32
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; A8: vsub.f32
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%0 = fmul float %a, %b
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%1 = fsub float %acc, %0
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ret float %1
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}
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define double @t2(double %acc, double %a, double %b) {
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entry:
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; VFP2: t2:
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; VFP2: vmls.f64
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; NEON: t2:
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; NEON: vmls.f64
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; A8: t2:
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; A8: vmul.f64
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; A8: vsub.f64
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%0 = fmul double %a, %b
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%1 = fsub double %acc, %0
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ret double %1
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}
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@ -1,23 +1,71 @@
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; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
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; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
|
||||
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
|
||||
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
|
||||
; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
|
||||
|
||||
define float @test1(float %acc, float %a, float %b) nounwind {
|
||||
; CHECK: vnmla.f32 s{{.*}}, s{{.*}}, s{{.*}}
|
||||
define float @t1(float %acc, float %a, float %b) nounwind {
|
||||
entry:
|
||||
; VFP2: t1:
|
||||
; VFP2: vnmla.f32
|
||||
|
||||
; NEON: t1:
|
||||
; NEON: vnmla.f32
|
||||
|
||||
; A8: t1:
|
||||
; A8: vnmul.f32 s0, s1, s0
|
||||
; A8: vsub.f32 d0, d0, d1
|
||||
%0 = fmul float %a, %b
|
||||
%1 = fsub float -0.0, %0
|
||||
%2 = fsub float %1, %acc
|
||||
ret float %2
|
||||
}
|
||||
|
||||
define float @test2(float %acc, float %a, float %b) nounwind {
|
||||
; CHECK: vnmla.f32 s{{.*}}, s{{.*}}, s{{.*}}
|
||||
define float @t2(float %acc, float %a, float %b) nounwind {
|
||||
entry:
|
||||
; VFP2: t2:
|
||||
; VFP2: vnmla.f32
|
||||
|
||||
; NEON: t2:
|
||||
; NEON: vnmla.f32
|
||||
|
||||
; A8: t2:
|
||||
; A8: vnmul.f32 s0, s1, s0
|
||||
; A8: vsub.f32 d0, d0, d1
|
||||
%0 = fmul float %a, %b
|
||||
%1 = fmul float -1.0, %0
|
||||
%2 = fsub float %1, %acc
|
||||
ret float %2
|
||||
}
|
||||
|
||||
define double @t3(double %acc, double %a, double %b) nounwind {
|
||||
entry:
|
||||
; VFP2: t3:
|
||||
; VFP2: vnmla.f64
|
||||
|
||||
; NEON: t3:
|
||||
; NEON: vnmla.f64
|
||||
|
||||
; A8: t3:
|
||||
; A8: vnmul.f64 d16, d16, d17
|
||||
; A8: vsub.f64 d16, d16, d17
|
||||
%0 = fmul double %a, %b
|
||||
%1 = fsub double -0.0, %0
|
||||
%2 = fsub double %1, %acc
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define double @t4(double %acc, double %a, double %b) nounwind {
|
||||
entry:
|
||||
; VFP2: t4:
|
||||
; VFP2: vnmla.f64
|
||||
|
||||
; NEON: t4:
|
||||
; NEON: vnmla.f64
|
||||
|
||||
; A8: t4:
|
||||
; A8: vnmul.f64 d16, d16, d17
|
||||
; A8: vsub.f64 d16, d16, d17
|
||||
%0 = fmul double %a, %b
|
||||
%1 = fmul double -1.0, %0
|
||||
%2 = fsub double %1, %acc
|
||||
ret double %2
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,14 +4,14 @@
|
|||
; constant offset addressing, so that each of the following stores
|
||||
; uses the same register.
|
||||
|
||||
; CHECK: vstr.32 s{{.*}}, [lr, #-128]
|
||||
; CHECK: vstr.32 s{{.*}}, [lr, #-96]
|
||||
; CHECK: vstr.32 s{{.*}}, [lr, #-64]
|
||||
; CHECK: vstr.32 s{{.*}}, [lr, #-32]
|
||||
; CHECK: vstr.32 s{{.*}}, [lr]
|
||||
; CHECK: vstr.32 s{{.*}}, [lr, #32]
|
||||
; CHECK: vstr.32 s{{.*}}, [lr, #64]
|
||||
; CHECK: vstr.32 s{{.*}}, [lr, #96]
|
||||
; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-128]
|
||||
; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-96]
|
||||
; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-64]
|
||||
; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-32]
|
||||
; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}]
|
||||
; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #32]
|
||||
; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #64]
|
||||
; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #96]
|
||||
|
||||
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
|
||||
|
||||
|
|
@ -627,7 +627,7 @@ bb24: ; preds = %bb23
|
|||
; in a register.
|
||||
|
||||
; CHECK: @ %bb24
|
||||
; CHECK: subs{{.*}} [[REGISTER:(r[0-9]+)|(lr)]], #1
|
||||
; CHECK: subs{{.*}} {{(r[0-9]+)|(lr)}}, #1
|
||||
; CHECK: bne.w
|
||||
|
||||
%92 = icmp eq i32 %tmp81, %indvar78 ; <i1> [#uses=1]
|
||||
|
|
|
|||
Loading…
Reference in New Issue