replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[XCore] Provide information about known zero bits of resource instructions. 

llvm-svn: 202393
This commit is contained in:
Richard Osborne 2014-02-27 13:20:06 +00:00
parent cb9272fe66
commit 2d3a2bee41
2 changed files with 80 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
llvm/lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -1770,6 +1770,34 @@ void XCoreTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
KnownZero.getBitWidth() - 1);
}
break;
case ISD::INTRINSIC_W_CHAIN:
{
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
switch (IntNo) {
case Intrinsic::xcore_getts:
// High bits are known to be zero.
KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
KnownZero.getBitWidth() - 16);
break;
case Intrinsic::xcore_int:
case Intrinsic::xcore_inct:
// High bits are known to be zero.
KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
KnownZero.getBitWidth() - 8);
break;
case Intrinsic::xcore_testct:
// Result is either 0 or 1.
KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
KnownZero.getBitWidth() - 1);
break;
case Intrinsic::xcore_testwct:
// Result is in the range 0 - 4.
KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
KnownZero.getBitWidth() - 3);
break;
}
}
break;
}
}

52
llvm/test/CodeGen/XCore/resources_combine.ll Normal file
View File

@ -0,0 +1,52 @@
; RUN: llc -march=xcore < %s | FileCheck %s
declare i32 @llvm.xcore.int.p1i8(i8 addrspace(1)* %r)
declare i32 @llvm.xcore.inct.p1i8(i8 addrspace(1)* %r)
declare i32 @llvm.xcore.testct.p1i8(i8 addrspace(1)* %r)
declare i32 @llvm.xcore.testwct.p1i8(i8 addrspace(1)* %r)
declare i32 @llvm.xcore.getts.p1i8(i8 addrspace(1)* %r)
define i32 @int(i8 addrspace(1)* %r) nounwind {
; CHECK-LABEL: int:
; CHECK: int r0, res[r0]
; CHECK-NEXT: retsp 0
%result = call i32 @llvm.xcore.int.p1i8(i8 addrspace(1)* %r)
%trunc = and i32 %result, 255
ret i32 %trunc
}
define i32 @inct(i8 addrspace(1)* %r) nounwind {
; CHECK-LABEL: inct:
; CHECK: inct r0, res[r0]
; CHECK-NEXT: retsp 0
%result = call i32 @llvm.xcore.inct.p1i8(i8 addrspace(1)* %r)
%trunc = and i32 %result, 255
ret i32 %trunc
}
define i32 @testct(i8 addrspace(1)* %r) nounwind {
; CHECK-LABEL: testct:
; CHECK: testct r0, res[r0]
; CHECK-NEXT: retsp 0
%result = call i32 @llvm.xcore.testct.p1i8(i8 addrspace(1)* %r)
%trunc = and i32 %result, 1
ret i32 %trunc
}
define i32 @testwct(i8 addrspace(1)* %r) nounwind {
; CHECK-LABEL: testwct:
; CHECK: testwct r0, res[r0]
; CHECK-NEXT: retsp 0
%result = call i32 @llvm.xcore.testwct.p1i8(i8 addrspace(1)* %r)
%trunc = and i32 %result, 7
ret i32 %trunc
}
define i32 @getts(i8 addrspace(1)* %r) nounwind {
; CHECK-LABEL: getts:
; CHECK: getts r0, res[r0]
; CHECK-NEXT: retsp 0
%result = call i32 @llvm.xcore.getts.p1i8(i8 addrspace(1)* %r)
%trunc = and i32 %result, 65535
ret i32 %result
}