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[ARM] GlobalISel: Mark shifts as legal for s32 

The new legalize combiner introduces shifts all over the place, so we
should support them sooner rather than later.

llvm-svn: 315064
This commit is contained in:
Diana Picus 2017-10-06 14:30:05 +00:00
parent c63ed222b8
commit 2c95730450
2 changed files with 82 additions and 0 deletions
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3
llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
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@ -80,6 +80,9 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
setAction({Op, 1, Ty}, Legal);
}
for (unsigned Op : {G_ASHR, G_LSHR, G_SHL})
setAction({Op, s32}, Legal);
setAction({G_GEP, p0}, Legal);
setAction({G_GEP, 1, s32}, Legal);

79
llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
View File

@ -27,6 +27,10 @@
define void @test_xor_s16() { ret void }
define void @test_xor_s32() { ret void }
define void @test_lshr_s32() { ret void }
define void @test_ashr_s32() { ret void }
define void @test_shl_s32() { ret void }
define void @test_load_from_stack() { ret void }
define void @test_legal_loads() #0 { ret void }
define void @test_legal_stores() #0 { ret void }
@ -563,6 +567,81 @@ body: |
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_lshr_s32
# CHECK-LABEL: name: test_lshr_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = G_LSHR %0, %1
; G_LSHR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}(s32) = G_LSHR {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_ashr_s32
# CHECK-LABEL: name: test_ashr_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = G_ASHR %0, %1
; G_ASHR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}(s32) = G_ASHR {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_shl_s32
# CHECK-LABEL: name: test_shl_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = G_SHL %0, %1
; G_SHL with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}(s32) = G_SHL {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_load_from_stack