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Add definition of 64-bit load upper immediate. 

llvm-svn: 143994
This commit is contained in:
Akira Hatanaka 2011-11-07 19:10:49 +00:00
parent 2f4480046b
commit 2b8d1f163f
2 changed files with 4 additions and 3 deletions
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1
llvm/lib/Target/Mips/Mips64InstrInfo.td
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@ -69,6 +69,7 @@ def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>;
def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>;
def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
/// Arithmetic Instructions (3-Operand, R-Type)
def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>;

6
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -334,8 +334,8 @@ class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
}
// Load Upper Imediate
class LoadUpper<bits<6> op, string instr_asm>:
FI<op, (outs CPURegs:$rt), (ins uimm16:$imm16),
class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
FI<op, (outs RC:$rt), (ins Imm:$imm16),
!strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
let rs = 0;
}
@ -680,7 +680,7 @@ def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
def LUi : LoadUpper<0x0f, "lui">;
def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
/// Arithmetic Instructions (3-Operand, R-Type)
def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;