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[NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter` 

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D119846
This commit is contained in:
Shao-Ce SUN 2022-02-16 13:09:59 +08:00
parent 314155eb8f
commit 2aed07e96c
57 changed files with 33 additions and 85 deletions
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4
bolt/include/bolt/Core/BinaryContext.h
View File

@ -1192,14 +1192,14 @@ public:
/*PIC=*/!HasFixedLoadAddress));
MCEInstance.LocalCtx->setObjectFileInfo(MCEInstance.LocalMOFI.get());
MCEInstance.MCE.reset(
TheTarget->createMCCodeEmitter(*MII, *MRI, *MCEInstance.LocalCtx));
TheTarget->createMCCodeEmitter(*MII, *MCEInstance.LocalCtx));
return MCEInstance;
}
/// Creating MCStreamer instance.
std::unique_ptr<MCStreamer>
createStreamer(llvm::raw_pwrite_stream &OS) const {
MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *Ctx);
MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, *Ctx);
MCAsmBackend *MAB =
TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions());
std::unique_ptr<MCObjectWriter> OW = MAB->createObjectWriter(OS);

2
bolt/lib/Core/BinaryContext.cpp
View File

@ -223,7 +223,7 @@ BinaryContext::createBinaryContext(const ObjectFile *File, bool IsPIC,
InstructionPrinter->setPrintImmHex(true);
std::unique_ptr<MCCodeEmitter> MCE(
TheTarget->createMCCodeEmitter(*MII, *MRI, *Ctx));
TheTarget->createMCCodeEmitter(*MII, *Ctx));
// Make sure we don't miss any output on core dumps.
outs().SetUnbuffered();

4
clang/tools/driver/cc1as_main.cpp
View File

@ -455,7 +455,7 @@ static bool ExecuteAssemblerImpl(AssemblerInvocation &Opts,
std::unique_ptr<MCCodeEmitter> CE;
if (Opts.ShowEncoding)
CE.reset(TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx));
CE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx));
std::unique_ptr<MCAsmBackend> MAB(
TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions));
@ -475,7 +475,7 @@ static bool ExecuteAssemblerImpl(AssemblerInvocation &Opts,
}
std::unique_ptr<MCCodeEmitter> CE(
TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx));
TheTarget->createMCCodeEmitter(*MCII, Ctx));
std::unique_ptr<MCAsmBackend> MAB(
TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions));
assert(MAB && "Unable to create asm backend!");

5
llvm/include/llvm/MC/TargetRegistry.h
View File

@ -175,7 +175,6 @@ public:
const MCInstrInfo &MII,
const MCRegisterInfo &MRI);
using MCCodeEmitterCtorTy = MCCodeEmitter *(*)(const MCInstrInfo &II,
const MCRegisterInfo &MRI,
MCContext &Ctx);
using ELFStreamerCtorTy =
MCStreamer *(*)(const Triple &T, MCContext &Ctx,
@ -506,11 +505,10 @@ public:
/// createMCCodeEmitter - Create a target specific code emitter.
MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
const MCRegisterInfo &MRI,
MCContext &Ctx) const {
if (!MCCodeEmitterCtorFn)
return nullptr;
return MCCodeEmitterCtorFn(II, MRI, Ctx);
return MCCodeEmitterCtorFn(II, Ctx);
}
/// Create a target specific MCStreamer.
@ -1360,7 +1358,6 @@ template <class MCCodeEmitterImpl> struct RegisterMCCodeEmitter {
private:
static MCCodeEmitter *Allocator(const MCInstrInfo & /*II*/,
const MCRegisterInfo & /*MRI*/,
MCContext & /*Ctx*/) {
return new MCCodeEmitterImpl();
}

7
llvm/lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -165,7 +165,7 @@ Expected<std::unique_ptr<MCStreamer>> LLVMTargetMachine::createMCStreamer(
// Create a code emitter if asked to show the encoding.
std::unique_ptr<MCCodeEmitter> MCE;
if (Options.MCOptions.ShowMCEncoding)
MCE.reset(getTarget().createMCCodeEmitter(MII, MRI, Context));
MCE.reset(getTarget().createMCCodeEmitter(MII, Context));
std::unique_ptr<MCAsmBackend> MAB(
getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions));
@ -180,7 +180,7 @@ Expected<std::unique_ptr<MCStreamer>> LLVMTargetMachine::createMCStreamer(
case CGFT_ObjectFile: {
// Create the code emitter for the target if it exists. If not, .o file
// emission fails.
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, Context);
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, Context);
if (!MCE)
return make_error<StringError>("createMCCodeEmitter failed",
inconvertibleErrorCode());
@ -260,8 +260,7 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
// emission fails.
const MCSubtargetInfo &STI = *getMCSubtargetInfo();
const MCRegisterInfo &MRI = *getMCRegisterInfo();
MCCodeEmitter *MCE =
getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx);
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getMCInstrInfo(), *Ctx);
MCAsmBackend *MAB =
getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
if (!MCE || !MAB)

2
llvm/lib/DWARFLinker/DWARFStreamer.cpp
View File

@ -68,7 +68,7 @@ bool DwarfStreamer::init(Triple TheTriple,
if (!MII)
return error("no instr info info for target " + TripleName, Context), false;
MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
MCE = TheTarget->createMCCodeEmitter(*MII, *MC);
if (!MCE)
return error("no code emitter for target " + TripleName, Context), false;

1
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
View File

@ -678,7 +678,6 @@ unsigned AArch64MCCodeEmitter::fixOneOperandFPComparison(
#include "AArch64GenMCCodeEmitter.inc"
MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new AArch64MCCodeEmitter(MCII, Ctx);
}

1
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
View File

@ -33,7 +33,6 @@ class MCTargetStreamer;
class Target;
MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createAArch64leAsmBackend(const Target &T,
const MCSubtargetInfo &STI,

2
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
View File

@ -240,7 +240,7 @@ void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) {
raw_svector_ostream CodeStream(CodeBytes);
std::unique_ptr<MCCodeEmitter> InstEmitter(createSIMCCodeEmitter(
*STI.getInstrInfo(), *OutContext.getRegisterInfo(), OutContext));
*STI.getInstrInfo(), OutContext));
InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI);
assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));

1
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
View File

@ -33,7 +33,6 @@ enum AMDGPUDwarfFlavour : unsigned { Wave64 = 0, Wave32 = 1 };
MCRegisterInfo *createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour);
MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createAMDGPUAsmBackend(const Target &T,

3
llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
View File

@ -85,9 +85,8 @@ enum FCInstr {
};
MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new R600MCCodeEmitter(MCII, MRI);
return new R600MCCodeEmitter(MCII, *Ctx.getRegisterInfo());
}
void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,

1
llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCTargetDesc.h
View File

@ -24,7 +24,6 @@ class MCInstrInfo;
class MCRegisterInfo;
MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCInstrInfo *createR600MCInstrInfo();

8
llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
View File

@ -37,9 +37,8 @@ class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
const MCSubtargetInfo &STI) const;
public:
SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
MCContext &ctx)
: AMDGPUMCCodeEmitter(mcii), MRI(mri) {}
SIMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
: AMDGPUMCCodeEmitter(mcii), MRI(*ctx.getRegisterInfo()) {}
SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete;
@ -82,9 +81,8 @@ private:
} // end anonymous namespace
MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new SIMCCodeEmitter(MCII, MRI, Ctx);
return new SIMCCodeEmitter(MCII, Ctx);
}
// Returns the encoding value to use if the given integer is an integer inline

2
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -2006,13 +2006,11 @@ getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
#include "ARMGenMCCodeEmitter.inc"
MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new ARMMCCodeEmitter(MCII, Ctx, true);
}
MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new ARMMCCodeEmitter(MCII, Ctx, false);
}

2
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
View File

@ -73,11 +73,9 @@ MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
const MCSubtargetInfo &STI);
MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,

1
llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
View File

@ -295,7 +295,6 @@ void AVRMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
}
MCCodeEmitter *createAVRMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new AVRMCCodeEmitter(MCII, Ctx);
}

1
llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h
View File

@ -33,7 +33,6 @@ MCInstrInfo *createAVRMCInstrInfo();
/// Creates a machine code emitter for AVR.
MCCodeEmitter *createAVRMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
/// Creates an assembly backend for AVR.

6
llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
View File

@ -73,15 +73,13 @@ private:
} // end anonymous namespace
MCCodeEmitter *llvm::createBPFMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new BPFMCCodeEmitter(MCII, MRI, true);
return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), true);
}
MCCodeEmitter *llvm::createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new BPFMCCodeEmitter(MCII, MRI, false);
return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), false);
}
unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,

3
llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
View File

@ -14,6 +14,7 @@
#define LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFMCTARGETDESC_H
#include "llvm/Config/config.h"
#include "llvm/MC/MCContext.h"
#include "llvm/Support/DataTypes.h"
#include <memory>
@ -30,10 +31,8 @@ class MCTargetOptions;
class Target;
MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI,

1
llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp
View File

@ -173,7 +173,6 @@ MCFixupKind CSKYMCCodeEmitter::getTargetFixup(const MCExpr *Expr) const {
}
MCCodeEmitter *llvm::createCSKYMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new CSKYMCCodeEmitter(Ctx, MCII);
}

1
llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h
View File

@ -35,7 +35,6 @@ MCAsmBackend *createCSKYAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCTargetOptions &Options);
MCCodeEmitter *createCSKYMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
} // namespace llvm

1
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
View File

@ -789,7 +789,6 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
}
MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
MCRegisterInfo const &MRI,
MCContext &MCT) {
return new HexagonMCCodeEmitter(MII, MCT);
}

1
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
View File

@ -85,7 +85,6 @@ namespace Hexagon_MC {
}
MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &MCT);
MCAsmBackend *createHexagonAsmBackend(const Target &T,

1
llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp
View File

@ -304,7 +304,6 @@ unsigned LanaiMCCodeEmitter::getBranchTargetOpValue(
llvm::MCCodeEmitter *
llvm::createLanaiMCCodeEmitter(const MCInstrInfo &InstrInfo,
const MCRegisterInfo & /*MRI*/,
MCContext &context) {
return new LanaiMCCodeEmitter(InstrInfo, context);
}

1
llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h
View File

@ -27,7 +27,6 @@ class MCSubtargetInfo;
class Target;
MCCodeEmitter *createLanaiMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI,

1
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
View File

@ -88,7 +88,6 @@ void LoongArchMCCodeEmitter::encodeInstruction(
}
MCCodeEmitter *llvm::createLoongArchMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new LoongArchMCCodeEmitter(Ctx, MCII);
}

1
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.h
View File

@ -28,7 +28,6 @@ class MCSubtargetInfo;
class Target;
MCCodeEmitter *createLoongArchMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createLoongArchAsmBackend(const Target &T,

1
llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp
View File

@ -566,7 +566,6 @@ void M68kMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
}
MCCodeEmitter *llvm::createM68kMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new M68kMCCodeEmitter(MCII, Ctx);
}

1
llvm/lib/Target/M68k/MCTargetDesc/M68kMCTargetDesc.h
View File

@ -38,7 +38,6 @@ MCAsmBackend *createM68kAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCTargetOptions &Options);
MCCodeEmitter *createM68kMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
/// Construct an M68k ELF object writer.

3
llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp
View File

@ -167,7 +167,7 @@ unsigned MSP430MCCodeEmitter::getCGImmOpValue(const MCInst &MI, unsigned Op,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(Op);
assert(MO.isImm() && "Expr operand expected");
int64_t Imm = MO.getImm();
switch (Imm) {
default:
@ -200,7 +200,6 @@ unsigned MSP430MCCodeEmitter::getCCOpValue(const MCInst &MI, unsigned Op,
}
MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new MSP430MCCodeEmitter(Ctx, MCII);
}

1
llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h
View File

@ -31,7 +31,6 @@ class MCTargetStreamer;
/// Creates a machine code emitter for MSP430.
MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createMSP430MCAsmBackend(const Target &T,

2
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -42,13 +42,11 @@ using namespace llvm;
namespace llvm {
MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new MipsMCCodeEmitter(MCII, Ctx, false);
}
MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new MipsMCCodeEmitter(MCII, Ctx, true);
}

2
llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
View File

@ -31,10 +31,8 @@ class Target;
class Triple;
MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI,

1
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
View File

@ -34,7 +34,6 @@ using namespace llvm;
STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new PPCMCCodeEmitter(MCII, Ctx);
}

1
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
View File

@ -34,7 +34,6 @@ class MCTargetOptions;
class Target;
MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,

1
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
View File

@ -94,7 +94,6 @@ private:
} // end anonymous namespace
MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new RISCVMCCodeEmitter(Ctx, MCII);
}

1
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
View File

@ -29,7 +29,6 @@ class MCSubtargetInfo;
class Target;
MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,

1
llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
View File

@ -253,7 +253,6 @@ getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
#include "SparcGenMCCodeEmitter.inc"
MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new SparcMCCodeEmitter(MCII, Ctx);
}

1
llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
View File

@ -29,7 +29,6 @@ class MCTargetOptions;
class Target;
MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,

1
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
View File

@ -328,7 +328,6 @@ SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
#include "SystemZGenMCCodeEmitter.inc"
MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new SystemZMCCodeEmitter(MCII, Ctx);
}

1
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
View File

@ -78,7 +78,6 @@ inline unsigned getRegAsVR128(unsigned Reg) {
} // end namespace SystemZMC
MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createSystemZMCAsmBackend(const Target &T,

1
llvm/lib/Target/VE/MCTargetDesc/VEMCCodeEmitter.cpp
View File

@ -159,7 +159,6 @@ uint64_t VEMCCodeEmitter::getRDOpValue(const MCInst &MI, unsigned OpNo,
#include "VEGenMCCodeEmitter.inc"
MCCodeEmitter *llvm::createVEMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new VEMCCodeEmitter(MCII, Ctx);
}

3
llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h
View File

@ -28,8 +28,7 @@ class MCSubtargetInfo;
class MCTargetOptions;
class Target;
MCCodeEmitter *createVEMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, MCContext &Ctx);
MCCodeEmitter *createVEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx);
MCAsmBackend *createVEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options);

1
llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
View File

@ -62,7 +62,6 @@ static MCInstPrinter *createMCInstPrinter(const Triple & /*T*/,
}
static MCCodeEmitter *createCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo & /*MRI*/,
MCContext &Ctx) {
return createWebAssemblyMCCodeEmitter(MCII);
}

1
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@ -1843,7 +1843,6 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
}
MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new X86MCCodeEmitter(MCII, Ctx);
}

1
llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
View File

@ -70,7 +70,6 @@ MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
}
MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createX86_32AsmBackend(const Target &T,

3
llvm/lib/Target/X86/X86AsmPrinter.cpp
View File

@ -60,8 +60,7 @@ bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
SMShadowTracker.startFunction(MF);
CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
*Subtarget->getInstrInfo(), *Subtarget->getRegisterInfo(),
MF.getContext()));
*Subtarget->getInstrInfo(), MF.getContext()));
EmitFPOData =
Subtarget->isTargetWin32() && MF.getMMI().getModule()->getCodeViewFlag();

2
llvm/tools/llvm-dwp/llvm-dwp.cpp
View File

@ -165,7 +165,7 @@ int main(int argc, char **argv) {
if (!MII)
return error("no instr info info for target " + TripleName, Context);
MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, MC);
MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, MC);
if (!MCE)
return error("no code emitter for target " + TripleName, Context);

3
llvm/tools/llvm-exegesis/lib/LlvmState.cpp
View File

@ -67,8 +67,7 @@ bool LLVMState::canAssemble(const MCInst &Inst) const {
TheTargetMachine->getMCSubtargetInfo());
std::unique_ptr<const MCCodeEmitter> CodeEmitter(
TheTargetMachine->getTarget().createMCCodeEmitter(
*TheTargetMachine->getMCInstrInfo(), *TheTargetMachine->getMCRegisterInfo(),
Context));
*TheTargetMachine->getMCInstrInfo(), Context));
assert(CodeEmitter && "unable to create code emitter");
SmallVector<char, 16> Tmp;
raw_svector_ostream OS(Tmp);

2
llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
View File

@ -229,7 +229,7 @@ int AssembleOneInput(const uint8_t *Data, size_t Size) {
OS = BOS.get();
}
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx);
MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions);
Str.reset(TheTarget->createMCObjectStreamer(
TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB),

4
llvm/tools/llvm-mc/llvm-mc.cpp
View File

@ -541,7 +541,7 @@ int main(int argc, char **argv) {
// Set up the AsmStreamer.
std::unique_ptr<MCCodeEmitter> CE;
if (ShowEncoding)
CE.reset(TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx));
CE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx));
std::unique_ptr<MCAsmBackend> MAB(
TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions));
@ -561,7 +561,7 @@ int main(int argc, char **argv) {
OS = BOS.get();
}
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx);
MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions);
Str.reset(TheTarget->createMCObjectStreamer(
TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB),

2
llvm/tools/llvm-mca/llvm-mca.cpp
View File

@ -479,7 +479,7 @@ int main(int argc, char **argv) {
unsigned RegionIdx = 0;
std::unique_ptr<MCCodeEmitter> MCE(
TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx));
TheTarget->createMCCodeEmitter(*MCII, Ctx));
assert(MCE && "Unable to create code emitter!");
std::unique_ptr<MCAsmBackend> MAB(TheTarget->createMCAsmBackend(

4
llvm/tools/llvm-ml/llvm-ml.cpp
View File

@ -377,7 +377,7 @@ int main(int Argc, char **Argv) {
// Set up the AsmStreamer.
std::unique_ptr<MCCodeEmitter> CE;
if (InputArgs.hasArg(OPT_show_encoding))
CE.reset(TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx));
CE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx));
std::unique_ptr<MCAsmBackend> MAB(
TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions));
@ -395,7 +395,7 @@ int main(int Argc, char **Argv) {
OS = BOS.get();
}
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx);
MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions);
Str.reset(TheTarget->createMCObjectStreamer(
TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB),

2
llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
View File

@ -106,7 +106,7 @@ DWARFExpressionCopyBytesTest::createStreamer(raw_pwrite_stream &OS) {
Res.Ctx->setObjectFileInfo(Res.MOFI.get());
Res.MII.reset(TheTarget->createMCInstrInfo());
MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *MRI, *Res.Ctx);
MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx);
MCAsmBackend *MAB =
TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions());
std::unique_ptr<MCObjectWriter> OW = MAB->createObjectWriter(OS);

2
llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
View File

@ -464,7 +464,7 @@ llvm::Error dwarfgen::Generator::init(Triple TheTriple, uint16_t V) {
TLOF->Initialize(*MC, *TM);
MC->setObjectFileInfo(TLOF);
MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
MCE = TheTarget->createMCCodeEmitter(*MII, *MC);
if (!MCE)
return make_error<StringError>("no code emitter for target " + TripleName,
inconvertibleErrorCode());

3
llvm/unittests/MC/DwarfLineTableHeaders.cpp
View File

@ -77,8 +77,7 @@ public:
Res.Ctx->setObjectFileInfo(Res.MOFI.get());
Res.MII.reset(TheTarget->createMCInstrInfo());
MCCodeEmitter *MCE =
TheTarget->createMCCodeEmitter(*Res.MII, *MRI, *Res.Ctx);
MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx);
MCAsmBackend *MAB =
TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions());
std::unique_ptr<MCObjectWriter> OW = MAB->createObjectWriter(OS);

2
mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
View File

@ -377,7 +377,7 @@ SerializeToHsacoPass::assembleIsa(const std::string &isa) {
std::unique_ptr<llvm::MCStreamer> mcStreamer;
std::unique_ptr<llvm::MCInstrInfo> mcii(target->createMCInstrInfo());
llvm::MCCodeEmitter *ce = target->createMCCodeEmitter(*mcii, *mri, ctx);
llvm::MCCodeEmitter *ce = target->createMCCodeEmitter(*mcii, ctx);
llvm::MCAsmBackend *mab = target->createMCAsmBackend(*sti, *mri, mcOptions);
mcStreamer.reset(target->createMCObjectStreamer(
triple, ctx, std::unique_ptr<llvm::MCAsmBackend>(mab),