ARM64: always use i64 for the RHS of shift operations
Switching between i32 and i64 based on the LHS type is a good idea in theory, but pre-legalisation uses i64 regardless of our choice, leading to potential ISel errors. Should fix PR19294. llvm-svn: 205519
This commit is contained in:
Tim Northover
parent
caccac10b7
commit
2ad88d3aab
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@ -573,11 +573,6 @@ void ARM64TargetLowering::computeMaskedBitsForTargetNode(
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}
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MVT ARM64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
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if (!LHSTy.isSimple())
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return MVT::i64;
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MVT SimpleVT = LHSTy.getSimpleVT();
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if (SimpleVT == MVT::i32)
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return MVT::i32;
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return MVT::i64;
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}
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@ -1534,10 +1529,10 @@ getARM64XALUOOp(ARM64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
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// check we have to arithmetic shift right the 32nd bit of the result by
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// 31 bits. Then we compare the result to the upper 32 bits.
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SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
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DAG.getConstant(32, MVT::i32));
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DAG.getConstant(32, MVT::i64));
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UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
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SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
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DAG.getConstant(31, MVT::i32));
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DAG.getConstant(31, MVT::i64));
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// It is important that LowerBits is last, otherwise the arithmetic
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// shift will not be folded into the compare (SUBS).
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SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
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@ -1550,7 +1545,7 @@ getARM64XALUOOp(ARM64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
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// pattern:
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// (i64 ARM64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
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SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
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DAG.getConstant(32, MVT::i32));
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DAG.getConstant(32, MVT::i64));
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SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
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Overflow =
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DAG.getNode(ARM64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
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@ -1564,7 +1559,7 @@ getARM64XALUOOp(ARM64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
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if (IsSigned) {
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SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
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SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
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DAG.getConstant(63, MVT::i32));
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DAG.getConstant(63, MVT::i64));
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// It is important that LowerBits is last, otherwise the arithmetic
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// shift will not be folded into the compare (SUBS).
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SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
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@ -6330,16 +6325,18 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
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if (VP1.isPowerOf2()) {
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// Multiplying by one less than a power of two, replace with a shift
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// and a subtract.
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SDValue ShiftedVal = DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
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DAG.getConstant(VP1.logBase2(), VT));
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SDValue ShiftedVal =
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DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
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DAG.getConstant(VP1.logBase2(), MVT::i64));
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return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
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}
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APInt VM1 = Value - 1;
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if (VM1.isPowerOf2()) {
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// Multiplying by one more than a power of two, replace with a shift
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// and an add.
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SDValue ShiftedVal = DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
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DAG.getConstant(VM1.logBase2(), VT));
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SDValue ShiftedVal =
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DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
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DAG.getConstant(VM1.logBase2(), MVT::i64));
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return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
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}
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}
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@ -440,57 +440,33 @@ def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
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let ParserMatchClass = Imm0_127Operand;
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}
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// NOTE: These imm0_N operands have to be of type i64 because i64 is the size
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// for all shift-amounts.
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// imm0_63 predicate - True if the immediate is in the range [0,63]
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// NOTE: This has to be of type i64 because i64 is the shift-amount-size
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// for X registers.
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def imm0_63 : Operand<i64>, ImmLeaf<i64, [{
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return ((uint64_t)Imm) < 64;
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}]> {
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let ParserMatchClass = Imm0_63Operand;
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}
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// imm0_31x predicate - True if the immediate is in the range [0,31]
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// NOTE: This has to be of type i64 because i64 is the shift-amount-size
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// for X registers.
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def imm0_31x : Operand<i64>, ImmLeaf<i64, [{
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// imm0_31 predicate - True if the immediate is in the range [0,31]
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def imm0_31 : Operand<i64>, ImmLeaf<i64, [{
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return ((uint64_t)Imm) < 32;
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}]> {
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let ParserMatchClass = Imm0_31Operand;
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}
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// imm0_15x predicate - True if the immediate is in the range [0,15]
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def imm0_15x : Operand<i64>, ImmLeaf<i64, [{
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// imm0_15 predicate - True if the immediate is in the range [0,15]
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def imm0_15 : Operand<i64>, ImmLeaf<i64, [{
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return ((uint64_t)Imm) < 16;
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}]> {
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let ParserMatchClass = Imm0_15Operand;
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}
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// imm0_7x predicate - True if the immediate is in the range [0,7]
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def imm0_7x : Operand<i64>, ImmLeaf<i64, [{
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return ((uint64_t)Imm) < 8;
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}]> {
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let ParserMatchClass = Imm0_7Operand;
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}
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// imm0_31 predicate - True if the immediate is in the range [0,31]
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// NOTE: This has to be of type i32 because i32 is the shift-amount-size
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// for W registers.
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def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
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return ((uint32_t)Imm) < 32;
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}]> {
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let ParserMatchClass = Imm0_31Operand;
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}
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// imm0_15 predicate - True if the immediate is in the range [0,15]
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def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
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return ((uint32_t)Imm) < 16;
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}]> {
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let ParserMatchClass = Imm0_15Operand;
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}
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// imm0_7 predicate - True if the immediate is in the range [0,7]
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def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
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return ((uint32_t)Imm) < 8;
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def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
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return ((uint64_t)Imm) < 8;
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}]> {
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let ParserMatchClass = Imm0_7Operand;
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}
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@ -1127,21 +1103,34 @@ multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
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}
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}
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class BaseShift<bits<2> shift_type, RegisterClass regtype,
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string asm, SDNode OpNode>
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class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
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SDPatternOperator OpNode = null_frag>
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: BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
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Sched<[WriteIS]> {
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let Inst{11-10} = shift_type;
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}
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multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
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def Wr : BaseShift<shift_type, GPR32, asm, OpNode> {
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def Wr : BaseShift<shift_type, GPR32, asm> {
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let Inst{31} = 0;
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}
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def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
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let Inst{31} = 1;
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}
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def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
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(!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
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(EXTRACT_SUBREG i64:$Rm, sub_32))>;
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def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
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def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
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def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
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}
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class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
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@ -1572,7 +1561,7 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode> {
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// Extract
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//---
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def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
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SDTCisSameAs<0, 3>]>;
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SDTCisPtrTy<3>]>;
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def ARM64Extr : SDNode<"ARM64ISD::EXTR", SDTA64EXTR>;
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class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
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@ -643,7 +643,7 @@ defm CLS : OneOperandData<0b101, "cls">;
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defm CLZ : OneOperandData<0b100, "clz", ctlz>;
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defm RBIT : OneOperandData<0b000, "rbit">;
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def REV16Wr : OneWRegData<0b001, "rev16",
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UnOpFrag<(rotr (bswap node:$LHS), (i32 16))>>;
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UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
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def REV16Xr : OneXRegData<0b001, "rev16",
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UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
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@ -670,7 +670,7 @@ def : InstAlias<"ror $dst, $src, $shift",
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def : InstAlias<"ror $dst, $src, $shift",
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(EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
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def : Pat<(rotr GPR32:$Rn, (i32 imm0_31:$imm)),
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def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
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(EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
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def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
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(EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
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@ -684,28 +684,28 @@ defm SBFM : BitfieldImm<0b00, "sbfm">;
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defm UBFM : BitfieldImm<0b10, "ubfm">;
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}
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def i32shift_a : Operand<i32>, SDNodeXForm<imm, [{
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def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
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uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
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return CurDAG->getTargetConstant(enc, MVT::i32);
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return CurDAG->getTargetConstant(enc, MVT::i64);
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}]>;
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def i32shift_b : Operand<i32>, SDNodeXForm<imm, [{
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def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
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uint64_t enc = 31 - N->getZExtValue();
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return CurDAG->getTargetConstant(enc, MVT::i32);
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return CurDAG->getTargetConstant(enc, MVT::i64);
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}]>;
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// min(7, 31 - shift_amt)
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def i32shift_sext_i8 : Operand<i32>, SDNodeXForm<imm, [{
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def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
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uint64_t enc = 31 - N->getZExtValue();
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enc = enc > 7 ? 7 : enc;
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return CurDAG->getTargetConstant(enc, MVT::i32);
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return CurDAG->getTargetConstant(enc, MVT::i64);
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}]>;
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// min(15, 31 - shift_amt)
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def i32shift_sext_i16 : Operand<i32>, SDNodeXForm<imm, [{
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def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
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uint64_t enc = 31 - N->getZExtValue();
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enc = enc > 15 ? 15 : enc;
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return CurDAG->getTargetConstant(enc, MVT::i32);
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return CurDAG->getTargetConstant(enc, MVT::i64);
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}]>;
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def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
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@ -739,15 +739,15 @@ def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(enc, MVT::i64);
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}]>;
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def : Pat<(shl GPR32:$Rn, (i32 imm0_31:$imm)),
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(UBFMWri GPR32:$Rn, (i32 (i32shift_a imm0_31:$imm)),
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(i32 (i32shift_b imm0_31:$imm)))>;
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def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
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(UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
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(i64 (i32shift_b imm0_31:$imm)))>;
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def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
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(UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
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(i64 (i64shift_b imm0_63:$imm)))>;
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let AddedComplexity = 10 in {
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def : Pat<(sra GPR32:$Rn, (i32 imm0_31:$imm)),
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def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
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(SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
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def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
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(SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
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@ -763,7 +763,7 @@ def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
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def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
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def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
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def : Pat<(srl GPR32:$Rn, (i32 imm0_31:$imm)),
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def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
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(UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
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def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
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(UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
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@ -4247,16 +4247,16 @@ def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
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def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
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def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
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def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i32 imm0_31:$imm)),
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(SBFMWri GPR32:$Rn, (i32 (i32shift_a imm0_31:$imm)),
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(i32 (i32shift_sext_i8 imm0_31:$imm)))>;
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def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
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(SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
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(i64 (i32shift_sext_i8 imm0_31:$imm)))>;
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def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
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(SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
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(i64 (i64shift_sext_i8 imm0_63:$imm)))>;
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def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i32 imm0_31:$imm)),
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(SBFMWri GPR32:$Rn, (i32 (i32shift_a imm0_31:$imm)),
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(i32 (i32shift_sext_i16 imm0_31:$imm)))>;
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def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
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(SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
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(i64 (i32shift_sext_i16 imm0_31:$imm)))>;
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def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
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(SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
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(i64 (i64shift_sext_i16 imm0_63:$imm)))>;
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@ -4273,19 +4273,19 @@ let AddedComplexity = 20 in {
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// We support all sext + sra combinations which preserve at least one bit of the
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// original value which is to be sign extended. E.g. we support shifts up to
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// bitwidth-1 bits.
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def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i32 imm0_7:$imm)),
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(SBFMWri GPR32:$Rn, (i32 imm0_7:$imm), 7)>;
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def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7x:$imm)),
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(SBFMXri GPR64:$Rn, (i64 imm0_7x:$imm), 7)>;
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def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
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(SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
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def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
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(SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
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def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i32 imm0_15:$imm)),
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(SBFMWri GPR32:$Rn, (i32 imm0_15:$imm), 15)>;
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def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15x:$imm)),
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(SBFMXri GPR64:$Rn, (i64 imm0_15x:$imm), 15)>;
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def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
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(SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
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def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
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(SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
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def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31x:$imm)),
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def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
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(SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
|
||||
(i64 imm0_31x:$imm), 31)>;
|
||||
(i64 imm0_31:$imm), 31)>;
|
||||
} // AddedComplexity = 20
|
||||
|
||||
// To truncate, we can simply extract from a subregister.
|
||||
|
|
|
|||
Loading…
Reference in New Issue