replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

R600/SI: Add double precision fsub pattern for SI 

Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186179
This commit is contained in:
Tom Stellard 2013-07-12 18:15:08 +00:00
parent ab8a8c84d4
commit 2a6a610516
3 changed files with 42 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
llvm/lib/Target/R600/SIISelLowering.cpp
View File

@ -296,6 +296,21 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MI->eraseFromParent(); MI->eraseFromParent();
break; break;
} }
case AMDGPU::V_SUB_F64: {
const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64),
MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addReg(MI->getOperand(2).getReg())
.addImm(0) /* src2 */
.addImm(0) /* ABS */
.addImm(0) /* CLAMP */
.addImm(0) /* OMOD */
.addImm(2); /* NEG */
MI->eraseFromParent();
break;
}
} }
return BB; return BB;
} }

17
llvm/lib/Target/R600/SIInstructions.td
View File

@ -1232,17 +1232,23 @@ def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
} // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
// This psuedo instruction takes a pointer as input and outputs a resource
// constant that can be used with the ADDR64 MUBUF instructions.
let usesCustomInserter = 1 in { let usesCustomInserter = 1 in {
// This psuedo instruction takes a pointer as input and outputs a resource
// constant that can be used with the ADDR64 MUBUF instructions.
def SI_ADDR64_RSRC : InstSI < def SI_ADDR64_RSRC : InstSI <
(outs SReg_128:$srsrc), (outs SReg_128:$srsrc),
(ins SReg_64:$ptr), (ins SReg_64:$ptr),
"", [] "", []
>; >;
def V_SUB_F64 : InstSI <
(outs VReg_64:$dst),
(ins VReg_64:$src0, VReg_64:$src1),
"V_SUB_F64 $dst, $src0, $src1",
[]
>;
} // end usesCustomInserter } // end usesCustomInserter
} // end IsCodeGenOnly, isPseudo } // end IsCodeGenOnly, isPseudo
@ -1271,6 +1277,11 @@ def : Pat <
$src0, $src1, $src2, $src3) $src0, $src1, $src2, $src3)
>; >;
def : Pat <
(f64 (fsub f64:$src0, f64:$src1)),
(V_SUB_F64 $src0, $src1)
>;
/********** ======================= **********/ /********** ======================= **********/
/********** Image sampling patterns **********/ /********** Image sampling patterns **********/
/********** ======================= **********/ /********** ======================= **********/

13
llvm/test/CodeGen/R600/fsub64.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s
; CHECK: @fsub_f64
; CHECK: V_ADD_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}, 0, 0, 0, 0, 2
define void @fsub_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
double addrspace(1)* %in2) {
%r0 = load double addrspace(1)* %in1
%r1 = load double addrspace(1)* %in2
%r2 = fsub double %r0, %r1
store double %r2, double addrspace(1)* %out
ret void
}