NEON scheduling info fix. vmov reg, reg are single cycle instructions.
llvm-svn: 115344
This commit is contained in:
Evan Cheng
parent
c93237c991
commit
2a5d764858
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@ -3177,7 +3177,7 @@ def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
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v2i64, v2i32, NEONvshlli>;
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// VSHRN : Vector Shift Right and Narrow
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defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
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defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VMOVN, "vshrn", "i",
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NEONvshrn>;
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// VRSHL : Vector Rounding Shift
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@ -3284,7 +3284,7 @@ class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
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[(set DPR:$dst, (Ty (vnegd DPR:$src)))]>;
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class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
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: N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
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IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
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IIC_VSHLiQ, OpcodeStr, Dt, "$dst, $src", "",
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[(set QPR:$dst, (Ty (vnegq QPR:$src)))]>;
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// VNEG : Vector Negate (integer)
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@ -3349,9 +3349,9 @@ def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
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let neverHasSideEffects = 1 in {
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def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
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N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
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N3RegFrm, IIC_VMOV, "vmov", "$dst, $src", "", []>;
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def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
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N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
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N3RegFrm, IIC_VMOV, "vmov", "$dst, $src", "", []>;
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// Pseudo vector move instructions for QQ and QQQQ registers. This should
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// be expanded after register allocation is completed.
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@ -3577,7 +3577,7 @@ class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
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class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy>
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: NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
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IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
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IIC_VMOVQ, OpcodeStr, Dt, "$dst, $src[$lane]",
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[(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
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imm:$lane)))]>;
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@ -3616,11 +3616,11 @@ def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
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def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
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(outs QPR:$dst), (ins SPR:$src),
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IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
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IIC_VMOVQ, "vdup", "32", "$dst, ${src:lane}", "",
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[(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
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// VMOVN : Vector Narrowing Move
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defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
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defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
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"vmovn", "i", trunc>;
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// VQMOVN : Vector Saturating Narrowing Move
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defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
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@ -3684,7 +3684,7 @@ class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
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[(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
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class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
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: N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
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(ins QPR:$src), IIC_VMOVD,
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(ins QPR:$src), IIC_VMOVQ,
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OpcodeStr, Dt, "$dst, $src", "",
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[(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
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@ -3707,7 +3707,7 @@ class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
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[(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
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class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
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: N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
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(ins QPR:$src), IIC_VMOVD,
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(ins QPR:$src), IIC_VMOVQ,
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OpcodeStr, Dt, "$dst, $src", "",
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[(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
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@ -3726,7 +3726,7 @@ class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
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[(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
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class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
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: N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
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(ins QPR:$src), IIC_VMOVD,
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(ins QPR:$src), IIC_VMOVQ,
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OpcodeStr, Dt, "$dst, $src", "",
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[(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
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@ -129,6 +129,7 @@ def IIC_VUNAD : InstrItinClass;
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def IIC_VUNAQ : InstrItinClass;
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def IIC_VBIND : InstrItinClass;
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def IIC_VBINQ : InstrItinClass;
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def IIC_VMOV : InstrItinClass;
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def IIC_VMOVImm : InstrItinClass;
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def IIC_VMOVD : InstrItinClass;
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def IIC_VMOVQ : InstrItinClass;
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@ -137,6 +138,7 @@ def IIC_VMOVID : InstrItinClass;
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def IIC_VMOVISL : InstrItinClass;
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def IIC_VMOVSI : InstrItinClass;
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def IIC_VMOVDI : InstrItinClass;
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def IIC_VMOVN : InstrItinClass;
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def IIC_VPERMD : InstrItinClass;
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def IIC_VPERMQ : InstrItinClass;
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def IIC_VPERMQ3 : InstrItinClass;
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@ -487,6 +487,10 @@ def CortexA8Itineraries : ProcessorItineraries<
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InstrItinData<IIC_VBINQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
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//
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// Move
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InstrItinData<IIC_VMOV, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_NPipe]>], [1, 1]>,
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//
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// Move Immediate
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InstrItinData<IIC_VMOVImm, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_NPipe]>], [3]>,
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@ -521,6 +525,10 @@ def CortexA8Itineraries : ProcessorItineraries<
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InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
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//
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// Vector narrow move
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InstrItinData<IIC_VMOVN , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_NPipe]>], [3, 1]>,
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//
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// Double-register Permute
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InstrItinData<IIC_VPERMD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
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@ -801,6 +801,14 @@ def CortexA9Itineraries : ProcessorItineraries<
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InstrStage<1, [A9_Pipe1]>,
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InstrStage<4, [A9_MUX0, A9_NPipe]>],
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[9, 3, 2, 1]>,
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//
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// Move
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InstrItinData<IIC_VMOV, [InstrStage<1, [A9_DRegsN], 0, Required>,
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InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
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InstrStage<1, [A9_Pipe1]>,
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InstrStage<1, [A9_MUX0, A9_NPipe]>],
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[1,1]>,
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//
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// Move Immediate
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InstrItinData<IIC_VMOVImm, [InstrStage<1, [A9_DRegsN], 0, Required>,
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@ -819,14 +827,12 @@ def CortexA9Itineraries : ProcessorItineraries<
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[2, 1]>,
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//
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// Quad-register Permute Move
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// Result written in N2, but that is relative to the last cycle of multicycle,
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// so we use 3 for those cases
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InstrItinData<IIC_VMOVQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
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// FIXME: all latencies are arbitrary, no information is available
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InstrStage<4, [A9_DRegsVFP], 0, Reserved>,
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InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
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InstrStage<1, [A9_Pipe1]>,
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InstrStage<2, [A9_MUX0, A9_NPipe]>],
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[3, 1]>,
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InstrStage<1, [A9_MUX0, A9_NPipe]>],
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[2, 1]>,
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//
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// Integer to Single-precision Move
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InstrItinData<IIC_VMOVIS , [InstrStage<1, [A9_DRegsN], 0, Required>,
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@ -869,6 +875,14 @@ def CortexA9Itineraries : ProcessorItineraries<
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[3, 1, 1]>,
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//
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// Vector narrow move
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InstrItinData<IIC_VMOVN, [InstrStage<1, [A9_DRegsN], 0, Required>,
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// Extra latency cycles since wbck is 6 cycles
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InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
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InstrStage<1, [A9_Pipe1]>,
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InstrStage<1, [A9_MUX0, A9_NPipe]>],
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[3, 1]>,
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//
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// Double-register FP Unary
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InstrItinData<IIC_VUNAD, [InstrStage<1, [A9_DRegsN], 0, Required>,
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// Extra latency cycles since wbck is 6 cycles
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