Reverting VLD1/VST1 base-updating/post-incrementing combining
This reverts patches 223862, 224198, 224203, and 224754, which were all related to the vector load/store combining and were reverted/reaplied a few times due to the same alignment problems we're seeing now. Further tests, mainly self-hosting Clang, will be needed to reapply this patch in the future. llvm-svn: 228129
This commit is contained in:
Renato Golin
parent
d1f606ff0f
commit
2a5c0a51ce
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@ -565,7 +565,6 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::FP_TO_SINT);
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setTargetDAGCombine(ISD::FP_TO_UINT);
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setTargetDAGCombine(ISD::FDIV);
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setTargetDAGCombine(ISD::LOAD);
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// It is legal to extload from v4i8 to v4i16 or v4i32.
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MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
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@ -8868,18 +8867,17 @@ static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
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DAG.getUNDEF(VT), NewMask.data());
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}
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/// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP,
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/// NEON load/store intrinsics, and generic vector load/stores, to merge
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/// base address updates.
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/// For generic load/stores, the memory type is assumed to be a vector.
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/// The caller is assumed to have checked legality.
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/// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
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/// NEON load/store intrinsics to merge base address updates.
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static SDValue CombineBaseUpdate(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
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return SDValue();
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SelectionDAG &DAG = DCI.DAG;
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bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
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N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
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bool isStore = N->getOpcode() == ISD::STORE;
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unsigned AddrOpIdx = ((isIntrinsic || isStore) ? 2 : 1);
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unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
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SDValue Addr = N->getOperand(AddrOpIdx);
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// Search for a use of the address operand that is an increment.
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@ -8940,10 +8938,6 @@ static SDValue CombineBaseUpdate(SDNode *N,
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case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
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case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
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case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
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case ISD::LOAD: NewOpc = ARMISD::VLD1_UPD;
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NumVecs = 1; isLaneOp = false; break;
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case ISD::STORE: NewOpc = ARMISD::VST1_UPD;
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NumVecs = 1; isLoad = false; isLaneOp = false; break;
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}
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}
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@ -8951,11 +8945,8 @@ static SDValue CombineBaseUpdate(SDNode *N,
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EVT VecTy;
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if (isLoad)
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VecTy = N->getValueType(0);
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else if (isIntrinsic)
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VecTy = N->getOperand(AddrOpIdx+1).getValueType();
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else
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VecTy = N->getOperand(1).getValueType();
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VecTy = N->getOperand(AddrOpIdx+1).getValueType();
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unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
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if (isLaneOp)
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NumBytes /= VecTy.getVectorNumElements();
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@ -8972,70 +8963,25 @@ static SDValue CombineBaseUpdate(SDNode *N,
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continue;
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}
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EVT AlignedVecTy = VecTy;
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// If this is a less-than-standard-aligned load/store, change the type to
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// match the standard alignment.
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// The alignment is overlooked when selecting _UPD variants; and it's
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// easier to introduce bitcasts here than fix that.
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// There are 3 ways to get to this base-update combine:
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// - intrinsics: they are assumed to be properly aligned (to the standard
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// alignment of the memory type), so we don't need to do anything.
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// - ARMISD::VLDx nodes: they are only generated from the aforementioned
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// intrinsics, so, likewise, there's nothing to do.
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// - generic load/store instructions: the alignment is specified as an
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// explicit operand, rather than implicitly as the standard alignment
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// of the memory type (like the intrisics). We need to change the
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// memory type to match the explicit alignment. That way, we don't
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// generate non-standard-aligned ARMISD::VLDx nodes.
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if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(N)) {
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unsigned Alignment = LSN->getAlignment();
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if (Alignment == 0)
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Alignment = 1;
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if (Alignment < VecTy.getScalarSizeInBits() / 8) {
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MVT EltTy = MVT::getIntegerVT(Alignment * 8);
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assert(NumVecs == 1 && "Unexpected multi-element generic load/store.");
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assert(!isLaneOp && "Unexpected generic load/store lane.");
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unsigned NumElts = NumBytes / (EltTy.getSizeInBits() / 8);
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AlignedVecTy = MVT::getVectorVT(EltTy, NumElts);
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}
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}
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// Create the new updating load/store node.
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// First, create an SDVTList for the new updating node's results.
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EVT Tys[6];
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unsigned NumResultVecs = (isLoad ? NumVecs : 0);
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unsigned n;
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for (n = 0; n < NumResultVecs; ++n)
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Tys[n] = AlignedVecTy;
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Tys[n] = VecTy;
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Tys[n++] = MVT::i32;
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Tys[n] = MVT::Other;
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SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
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// Then, gather the new node's operands.
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(N->getOperand(0)); // incoming chain
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Ops.push_back(N->getOperand(AddrOpIdx));
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Ops.push_back(Inc);
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if (StoreSDNode *StN = dyn_cast<StoreSDNode>(N)) {
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// Try to match the intrinsic's signature
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Ops.push_back(StN->getValue());
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Ops.push_back(DAG.getConstant(StN->getAlignment(), MVT::i32));
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} else {
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for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i)
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Ops.push_back(N->getOperand(i));
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for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
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Ops.push_back(N->getOperand(i));
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}
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// If this is a non-standard-aligned store, the penultimate operand is the
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// stored value. Bitcast it to the aligned type.
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if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) {
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SDValue &StVal = Ops[Ops.size()-2];
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StVal = DAG.getNode(ISD::BITCAST, SDLoc(N), AlignedVecTy, StVal);
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}
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MemSDNode *MemInt = cast<MemSDNode>(N);
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MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
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SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
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Ops, AlignedVecTy,
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Ops, MemInt->getMemoryVT(),
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MemInt->getMemOperand());
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// Update the uses.
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@ -9043,14 +8989,6 @@ static SDValue CombineBaseUpdate(SDNode *N,
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for (unsigned i = 0; i < NumResultVecs; ++i) {
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NewResults.push_back(SDValue(UpdN.getNode(), i));
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}
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// If this is an non-standard-aligned load, the first result is the loaded
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// value. Bitcast it to the expected result type.
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if (AlignedVecTy != VecTy && N->getOpcode() == ISD::LOAD) {
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SDValue &LdVal = NewResults[0];
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LdVal = DAG.getNode(ISD::BITCAST, SDLoc(N), VecTy, LdVal);
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}
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NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
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DCI.CombineTo(N, NewResults);
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DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
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@ -9060,14 +8998,6 @@ static SDValue CombineBaseUpdate(SDNode *N,
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return SDValue();
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}
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static SDValue PerformVLDCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
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return SDValue();
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return CombineBaseUpdate(N, DCI);
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}
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/// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
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/// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
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/// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
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@ -9181,18 +9111,6 @@ static SDValue PerformVDUPLANECombine(SDNode *N,
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return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
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}
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static SDValue PerformLOADCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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EVT VT = N->getValueType(0);
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// If this is a legal vector load, try to combine it into a VLD1_UPD.
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if (ISD::isNormalLoad(N) && VT.isVector() &&
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DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
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return CombineBaseUpdate(N, DCI);
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return SDValue();
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}
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/// PerformSTORECombine - Target-specific dag combine xforms for
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/// ISD::STORE.
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static SDValue PerformSTORECombine(SDNode *N,
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@ -9331,11 +9249,6 @@ static SDValue PerformSTORECombine(SDNode *N,
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St->getAAInfo());
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}
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// If this is a legal vector store, try to combine it into a VST1_UPD.
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if (ISD::isNormalStore(N) && VT.isVector() &&
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DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
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return CombineBaseUpdate(N, DCI);
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return SDValue();
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}
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@ -9929,11 +9842,10 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
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case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
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case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
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case ISD::LOAD: return PerformLOADCombine(N, DCI);
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case ARMISD::VLD2DUP:
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case ARMISD::VLD3DUP:
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case ARMISD::VLD4DUP:
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return PerformVLDCombine(N, DCI);
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return CombineBaseUpdate(N, DCI);
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case ARMISD::BUILD_VECTOR:
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return PerformARMBUILD_VECTORCombine(N, DCI);
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case ISD::INTRINSIC_VOID:
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@ -9953,7 +9865,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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case Intrinsic::arm_neon_vst2lane:
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case Intrinsic::arm_neon_vst3lane:
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case Intrinsic::arm_neon_vst4lane:
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return PerformVLDCombine(N, DCI);
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return CombineBaseUpdate(N, DCI);
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default: break;
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}
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break;
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@ -9,8 +9,8 @@
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define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {
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entry:
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; NO-REALIGN-LABEL: test1
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; NO-REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
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; NO-REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
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; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
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; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
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; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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@ -21,14 +21,16 @@ entry:
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]!
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
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%retval = alloca <16 x float>, align 16
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%0 = load <16 x float>* @T3_retval, align 16
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@ -42,8 +44,8 @@ define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {
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entry:
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; REALIGN-LABEL: test2
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; REALIGN: bfc sp, #0, #6
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; REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
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; REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
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; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
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; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
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; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
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; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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@ -63,7 +65,8 @@ entry:
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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; REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
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; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #16
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
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%retval = alloca <16 x float>, align 16
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%0 = load <16 x float>* @T3_retval, align 16
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@ -46,8 +46,10 @@ entry:
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; CHECK: movw [[REG2:r[0-9]+]], #16716
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; CHECK: movt [[REG2:r[0-9]+]], #72
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; CHECK: str [[REG2]], [r0, #32]
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
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; CHECK: adds r0, #16
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; CHECK: adds r1, #16
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
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@ -57,8 +59,10 @@ entry:
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define void @t3(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
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; CHECK: adds r0, #16
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; CHECK: adds r1, #16
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; CHECK: vld1.8 {d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}}, [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
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@ -69,8 +73,7 @@ define void @t4(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t4:
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; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
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; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]!
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; CHECK: strh [[REG5:r[0-9]+]], [r0]
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; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
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ret void
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}
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@ -1,253 +0,0 @@
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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target triple = "thumbv7s-apple-ios8.0.0"
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define <8 x i8> @load_v8i8(<8 x i8>** %ptr) {
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;CHECK-LABEL: load_v8i8:
|
||||
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <8 x i8>** %ptr
|
||||
%lA = load <8 x i8>* %A, align 1
|
||||
ret <8 x i8> %lA
|
||||
}
|
||||
|
||||
define <8 x i8> @load_v8i8_update(<8 x i8>** %ptr) {
|
||||
;CHECK-LABEL: load_v8i8_update:
|
||||
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <8 x i8>** %ptr
|
||||
%lA = load <8 x i8>* %A, align 1
|
||||
%inc = getelementptr <8 x i8>* %A, i38 1
|
||||
store <8 x i8>* %inc, <8 x i8>** %ptr
|
||||
ret <8 x i8> %lA
|
||||
}
|
||||
|
||||
define <4 x i16> @load_v4i16(<4 x i16>** %ptr) {
|
||||
;CHECK-LABEL: load_v4i16:
|
||||
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <4 x i16>** %ptr
|
||||
%lA = load <4 x i16>* %A, align 1
|
||||
ret <4 x i16> %lA
|
||||
}
|
||||
|
||||
define <4 x i16> @load_v4i16_update(<4 x i16>** %ptr) {
|
||||
;CHECK-LABEL: load_v4i16_update:
|
||||
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <4 x i16>** %ptr
|
||||
%lA = load <4 x i16>* %A, align 1
|
||||
%inc = getelementptr <4 x i16>* %A, i34 1
|
||||
store <4 x i16>* %inc, <4 x i16>** %ptr
|
||||
ret <4 x i16> %lA
|
||||
}
|
||||
|
||||
define <2 x i32> @load_v2i32(<2 x i32>** %ptr) {
|
||||
;CHECK-LABEL: load_v2i32:
|
||||
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <2 x i32>** %ptr
|
||||
%lA = load <2 x i32>* %A, align 1
|
||||
ret <2 x i32> %lA
|
||||
}
|
||||
|
||||
define <2 x i32> @load_v2i32_update(<2 x i32>** %ptr) {
|
||||
;CHECK-LABEL: load_v2i32_update:
|
||||
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x i32>** %ptr
|
||||
%lA = load <2 x i32>* %A, align 1
|
||||
%inc = getelementptr <2 x i32>* %A, i32 1
|
||||
store <2 x i32>* %inc, <2 x i32>** %ptr
|
||||
ret <2 x i32> %lA
|
||||
}
|
||||
|
||||
define <2 x float> @load_v2f32(<2 x float>** %ptr) {
|
||||
;CHECK-LABEL: load_v2f32:
|
||||
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <2 x float>** %ptr
|
||||
%lA = load <2 x float>* %A, align 1
|
||||
ret <2 x float> %lA
|
||||
}
|
||||
|
||||
define <2 x float> @load_v2f32_update(<2 x float>** %ptr) {
|
||||
;CHECK-LABEL: load_v2f32_update:
|
||||
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x float>** %ptr
|
||||
%lA = load <2 x float>* %A, align 1
|
||||
%inc = getelementptr <2 x float>* %A, i32 1
|
||||
store <2 x float>* %inc, <2 x float>** %ptr
|
||||
ret <2 x float> %lA
|
||||
}
|
||||
|
||||
define <1 x i64> @load_v1i64(<1 x i64>** %ptr) {
|
||||
;CHECK-LABEL: load_v1i64:
|
||||
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <1 x i64>** %ptr
|
||||
%lA = load <1 x i64>* %A, align 1
|
||||
ret <1 x i64> %lA
|
||||
}
|
||||
|
||||
define <1 x i64> @load_v1i64_update(<1 x i64>** %ptr) {
|
||||
;CHECK-LABEL: load_v1i64_update:
|
||||
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <1 x i64>** %ptr
|
||||
%lA = load <1 x i64>* %A, align 1
|
||||
%inc = getelementptr <1 x i64>* %A, i31 1
|
||||
store <1 x i64>* %inc, <1 x i64>** %ptr
|
||||
ret <1 x i64> %lA
|
||||
}
|
||||
|
||||
define <16 x i8> @load_v16i8(<16 x i8>** %ptr) {
|
||||
;CHECK-LABEL: load_v16i8:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <16 x i8>** %ptr
|
||||
%lA = load <16 x i8>* %A, align 1
|
||||
ret <16 x i8> %lA
|
||||
}
|
||||
|
||||
define <16 x i8> @load_v16i8_update(<16 x i8>** %ptr) {
|
||||
;CHECK-LABEL: load_v16i8_update:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <16 x i8>** %ptr
|
||||
%lA = load <16 x i8>* %A, align 1
|
||||
%inc = getelementptr <16 x i8>* %A, i316 1
|
||||
store <16 x i8>* %inc, <16 x i8>** %ptr
|
||||
ret <16 x i8> %lA
|
||||
}
|
||||
|
||||
define <8 x i16> @load_v8i16(<8 x i16>** %ptr) {
|
||||
;CHECK-LABEL: load_v8i16:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <8 x i16>** %ptr
|
||||
%lA = load <8 x i16>* %A, align 1
|
||||
ret <8 x i16> %lA
|
||||
}
|
||||
|
||||
define <8 x i16> @load_v8i16_update(<8 x i16>** %ptr) {
|
||||
;CHECK-LABEL: load_v8i16_update:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <8 x i16>** %ptr
|
||||
%lA = load <8 x i16>* %A, align 1
|
||||
%inc = getelementptr <8 x i16>* %A, i38 1
|
||||
store <8 x i16>* %inc, <8 x i16>** %ptr
|
||||
ret <8 x i16> %lA
|
||||
}
|
||||
|
||||
define <4 x i32> @load_v4i32(<4 x i32>** %ptr) {
|
||||
;CHECK-LABEL: load_v4i32:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <4 x i32>** %ptr
|
||||
%lA = load <4 x i32>* %A, align 1
|
||||
ret <4 x i32> %lA
|
||||
}
|
||||
|
||||
define <4 x i32> @load_v4i32_update(<4 x i32>** %ptr) {
|
||||
;CHECK-LABEL: load_v4i32_update:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <4 x i32>** %ptr
|
||||
%lA = load <4 x i32>* %A, align 1
|
||||
%inc = getelementptr <4 x i32>* %A, i34 1
|
||||
store <4 x i32>* %inc, <4 x i32>** %ptr
|
||||
ret <4 x i32> %lA
|
||||
}
|
||||
|
||||
define <4 x float> @load_v4f32(<4 x float>** %ptr) {
|
||||
;CHECK-LABEL: load_v4f32:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <4 x float>** %ptr
|
||||
%lA = load <4 x float>* %A, align 1
|
||||
ret <4 x float> %lA
|
||||
}
|
||||
|
||||
define <4 x float> @load_v4f32_update(<4 x float>** %ptr) {
|
||||
;CHECK-LABEL: load_v4f32_update:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <4 x float>** %ptr
|
||||
%lA = load <4 x float>* %A, align 1
|
||||
%inc = getelementptr <4 x float>* %A, i34 1
|
||||
store <4 x float>* %inc, <4 x float>** %ptr
|
||||
ret <4 x float> %lA
|
||||
}
|
||||
|
||||
define <2 x i64> @load_v2i64(<2 x i64>** %ptr) {
|
||||
;CHECK-LABEL: load_v2i64:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <2 x i64>** %ptr
|
||||
%lA = load <2 x i64>* %A, align 1
|
||||
ret <2 x i64> %lA
|
||||
}
|
||||
|
||||
define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) {
|
||||
;CHECK-LABEL: load_v2i64_update:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x i64>** %ptr
|
||||
%lA = load <2 x i64>* %A, align 1
|
||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||
ret <2 x i64> %lA
|
||||
}
|
||||
|
||||
; Make sure we change the type to match alignment if necessary.
|
||||
define <2 x i64> @load_v2i64_update_aligned2(<2 x i64>** %ptr) {
|
||||
;CHECK-LABEL: load_v2i64_update_aligned2:
|
||||
;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x i64>** %ptr
|
||||
%lA = load <2 x i64>* %A, align 2
|
||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||
ret <2 x i64> %lA
|
||||
}
|
||||
|
||||
define <2 x i64> @load_v2i64_update_aligned4(<2 x i64>** %ptr) {
|
||||
;CHECK-LABEL: load_v2i64_update_aligned4:
|
||||
;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x i64>** %ptr
|
||||
%lA = load <2 x i64>* %A, align 4
|
||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||
ret <2 x i64> %lA
|
||||
}
|
||||
|
||||
define <2 x i64> @load_v2i64_update_aligned8(<2 x i64>** %ptr) {
|
||||
;CHECK-LABEL: load_v2i64_update_aligned8:
|
||||
;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:64]!
|
||||
%A = load <2 x i64>** %ptr
|
||||
%lA = load <2 x i64>* %A, align 8
|
||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||
ret <2 x i64> %lA
|
||||
}
|
||||
|
||||
define <2 x i64> @load_v2i64_update_aligned16(<2 x i64>** %ptr) {
|
||||
;CHECK-LABEL: load_v2i64_update_aligned16:
|
||||
;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
|
||||
%A = load <2 x i64>** %ptr
|
||||
%lA = load <2 x i64>* %A, align 16
|
||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||
ret <2 x i64> %lA
|
||||
}
|
||||
|
||||
; Make sure we don't break smaller-than-dreg extloads.
|
||||
define <4 x i32> @zextload_v8i8tov8i32(<4 x i8>** %ptr) {
|
||||
;CHECK-LABEL: zextload_v8i8tov8i32:
|
||||
;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [{{r[0-9]+}}:32]
|
||||
;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
|
||||
;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
|
||||
%A = load <4 x i8>** %ptr
|
||||
%lA = load <4 x i8>* %A, align 4
|
||||
%zlA = zext <4 x i8> %lA to <4 x i32>
|
||||
ret <4 x i32> %zlA
|
||||
}
|
||||
|
||||
define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) {
|
||||
;CHECK-LABEL: zextload_v8i8tov8i32_fake_update:
|
||||
;CHECK: ldr.w r[[PTRREG:[0-9]+]], [r0]
|
||||
;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r[[PTRREG]]:32]
|
||||
;CHECK: add.w r[[INCREG:[0-9]+]], r[[PTRREG]], #16
|
||||
;CHECK: str.w r[[INCREG]], [r0]
|
||||
;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
|
||||
;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
|
||||
%A = load <4 x i8>** %ptr
|
||||
%lA = load <4 x i8>* %A, align 4
|
||||
%inc = getelementptr <4 x i8>* %A, i38 4
|
||||
store <4 x i8>* %inc, <4 x i8>** %ptr
|
||||
%zlA = zext <4 x i8> %lA to <4 x i32>
|
||||
ret <4 x i32> %zlA
|
||||
}
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
; RUN: llc < %s | FileCheck %s
|
||||
|
||||
target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
|
||||
target triple = "thumbv7s-apple-ios8.0.0"
|
||||
|
||||
define void @store_v8i8(<8 x i8>** %ptr, <8 x i8> %val) {
|
||||
;CHECK-LABEL: store_v8i8:
|
||||
;CHECK: str r1, [r0]
|
||||
%A = load <8 x i8>** %ptr
|
||||
store <8 x i8> %val, <8 x i8>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v8i8_update(<8 x i8>** %ptr, <8 x i8> %val) {
|
||||
;CHECK-LABEL: store_v8i8_update:
|
||||
;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <8 x i8>** %ptr
|
||||
store <8 x i8> %val, <8 x i8>* %A, align 1
|
||||
%inc = getelementptr <8 x i8>* %A, i38 1
|
||||
store <8 x i8>* %inc, <8 x i8>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v4i16(<4 x i16>** %ptr, <4 x i16> %val) {
|
||||
;CHECK-LABEL: store_v4i16:
|
||||
;CHECK: str r1, [r0]
|
||||
%A = load <4 x i16>** %ptr
|
||||
store <4 x i16> %val, <4 x i16>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v4i16_update(<4 x i16>** %ptr, <4 x i16> %val) {
|
||||
;CHECK-LABEL: store_v4i16_update:
|
||||
;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <4 x i16>** %ptr
|
||||
store <4 x i16> %val, <4 x i16>* %A, align 1
|
||||
%inc = getelementptr <4 x i16>* %A, i34 1
|
||||
store <4 x i16>* %inc, <4 x i16>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2i32(<2 x i32>** %ptr, <2 x i32> %val) {
|
||||
;CHECK-LABEL: store_v2i32:
|
||||
;CHECK: str r1, [r0]
|
||||
%A = load <2 x i32>** %ptr
|
||||
store <2 x i32> %val, <2 x i32>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2i32_update(<2 x i32>** %ptr, <2 x i32> %val) {
|
||||
;CHECK-LABEL: store_v2i32_update:
|
||||
;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x i32>** %ptr
|
||||
store <2 x i32> %val, <2 x i32>* %A, align 1
|
||||
%inc = getelementptr <2 x i32>* %A, i32 1
|
||||
store <2 x i32>* %inc, <2 x i32>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2f32(<2 x float>** %ptr, <2 x float> %val) {
|
||||
;CHECK-LABEL: store_v2f32:
|
||||
;CHECK: str r1, [r0]
|
||||
%A = load <2 x float>** %ptr
|
||||
store <2 x float> %val, <2 x float>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2f32_update(<2 x float>** %ptr, <2 x float> %val) {
|
||||
;CHECK-LABEL: store_v2f32_update:
|
||||
;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x float>** %ptr
|
||||
store <2 x float> %val, <2 x float>* %A, align 1
|
||||
%inc = getelementptr <2 x float>* %A, i32 1
|
||||
store <2 x float>* %inc, <2 x float>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v1i64(<1 x i64>** %ptr, <1 x i64> %val) {
|
||||
;CHECK-LABEL: store_v1i64:
|
||||
;CHECK: str r1, [r0]
|
||||
%A = load <1 x i64>** %ptr
|
||||
store <1 x i64> %val, <1 x i64>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v1i64_update(<1 x i64>** %ptr, <1 x i64> %val) {
|
||||
;CHECK-LABEL: store_v1i64_update:
|
||||
;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <1 x i64>** %ptr
|
||||
store <1 x i64> %val, <1 x i64>* %A, align 1
|
||||
%inc = getelementptr <1 x i64>* %A, i31 1
|
||||
store <1 x i64>* %inc, <1 x i64>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v16i8(<16 x i8>** %ptr, <16 x i8> %val) {
|
||||
;CHECK-LABEL: store_v16i8:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <16 x i8>** %ptr
|
||||
store <16 x i8> %val, <16 x i8>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v16i8_update(<16 x i8>** %ptr, <16 x i8> %val) {
|
||||
;CHECK-LABEL: store_v16i8_update:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <16 x i8>** %ptr
|
||||
store <16 x i8> %val, <16 x i8>* %A, align 1
|
||||
%inc = getelementptr <16 x i8>* %A, i316 1
|
||||
store <16 x i8>* %inc, <16 x i8>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v8i16(<8 x i16>** %ptr, <8 x i16> %val) {
|
||||
;CHECK-LABEL: store_v8i16:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <8 x i16>** %ptr
|
||||
store <8 x i16> %val, <8 x i16>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v8i16_update(<8 x i16>** %ptr, <8 x i16> %val) {
|
||||
;CHECK-LABEL: store_v8i16_update:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <8 x i16>** %ptr
|
||||
store <8 x i16> %val, <8 x i16>* %A, align 1
|
||||
%inc = getelementptr <8 x i16>* %A, i38 1
|
||||
store <8 x i16>* %inc, <8 x i16>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v4i32(<4 x i32>** %ptr, <4 x i32> %val) {
|
||||
;CHECK-LABEL: store_v4i32:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <4 x i32>** %ptr
|
||||
store <4 x i32> %val, <4 x i32>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v4i32_update(<4 x i32>** %ptr, <4 x i32> %val) {
|
||||
;CHECK-LABEL: store_v4i32_update:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <4 x i32>** %ptr
|
||||
store <4 x i32> %val, <4 x i32>* %A, align 1
|
||||
%inc = getelementptr <4 x i32>* %A, i34 1
|
||||
store <4 x i32>* %inc, <4 x i32>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v4f32(<4 x float>** %ptr, <4 x float> %val) {
|
||||
;CHECK-LABEL: store_v4f32:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <4 x float>** %ptr
|
||||
store <4 x float> %val, <4 x float>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v4f32_update(<4 x float>** %ptr, <4 x float> %val) {
|
||||
;CHECK-LABEL: store_v4f32_update:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <4 x float>** %ptr
|
||||
store <4 x float> %val, <4 x float>* %A, align 1
|
||||
%inc = getelementptr <4 x float>* %A, i34 1
|
||||
store <4 x float>* %inc, <4 x float>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2i64(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||
;CHECK-LABEL: store_v2i64:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <2 x i64>** %ptr
|
||||
store <2 x i64> %val, <2 x i64>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2i64_update(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||
;CHECK-LABEL: store_v2i64_update:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x i64>** %ptr
|
||||
store <2 x i64> %val, <2 x i64>* %A, align 1
|
||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2i64_update_aligned2(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||
;CHECK-LABEL: store_v2i64_update_aligned2:
|
||||
;CHECK: vst1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x i64>** %ptr
|
||||
store <2 x i64> %val, <2 x i64>* %A, align 2
|
||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2i64_update_aligned4(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||
;CHECK-LABEL: store_v2i64_update_aligned4:
|
||||
;CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x i64>** %ptr
|
||||
store <2 x i64> %val, <2 x i64>* %A, align 4
|
||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2i64_update_aligned8(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||
;CHECK-LABEL: store_v2i64_update_aligned8:
|
||||
;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:64]!
|
||||
%A = load <2 x i64>** %ptr
|
||||
store <2 x i64> %val, <2 x i64>* %A, align 8
|
||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2i64_update_aligned16(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||
;CHECK-LABEL: store_v2i64_update_aligned16:
|
||||
;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
|
||||
%A = load <2 x i64>** %ptr
|
||||
store <2 x i64> %val, <2 x i64>* %A, align 16
|
||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) {
|
||||
;CHECK-LABEL: truncstore_v4i32tov4i8:
|
||||
;CHECK: ldr.w r9, [sp]
|
||||
;CHECK: vmov {{d[0-9]+}}, r3, r9
|
||||
;CHECK: vmov {{d[0-9]+}}, r1, r2
|
||||
;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}}
|
||||
;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}}
|
||||
;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]
|
||||
;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32]
|
||||
%A = load <4 x i8>** %ptr
|
||||
%trunc = trunc <4 x i32> %val to <4 x i8>
|
||||
store <4 x i8> %trunc, <4 x i8>* %A, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @truncstore_v4i32tov4i8_fake_update(<4 x i8>** %ptr, <4 x i32> %val) {
|
||||
;CHECK-LABEL: truncstore_v4i32tov4i8_fake_update:
|
||||
;CHECK: ldr.w r9, [sp]
|
||||
;CHECK: vmov {{d[0-9]+}}, r3, r9
|
||||
;CHECK: vmov {{d[0-9]+}}, r1, r2
|
||||
;CHECK: movs [[IMM16:r[0-9]+]], #16
|
||||
;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}}
|
||||
;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}}
|
||||
;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]
|
||||
;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32], [[IMM16]]
|
||||
;CHECK: str r[[PTRREG]], [r0]
|
||||
%A = load <4 x i8>** %ptr
|
||||
%trunc = trunc <4 x i32> %val to <4 x i8>
|
||||
store <4 x i8> %trunc, <4 x i8>* %A, align 4
|
||||
%inc = getelementptr <4 x i8>* %A, i38 4
|
||||
store <4 x i8>* %inc, <4 x i8>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
|
@ -201,7 +201,7 @@ for.end: ; preds = %for.body
|
|||
;
|
||||
; Currently we have three extra add.w's that keep the store address
|
||||
; live past the next increment because ISEL is unfortunately undoing
|
||||
; the store chain. ISEL also fails to convert all but one of the stores to
|
||||
; the store chain. ISEL also fails to convert the stores to
|
||||
; post-increment addressing. However, the loads should use
|
||||
; post-increment addressing, no add's or add.w's beyond the three
|
||||
; mentioned. Most importantly, there should be no spills or reloads!
|
||||
|
|
@ -210,7 +210,7 @@ for.end: ; preds = %for.body
|
|||
; A9: %.lr.ph
|
||||
; A9-NOT: lsl.w
|
||||
; A9-NOT: {{ldr|str|adds|add r}}
|
||||
; A9: vst1.8 {{.*}} [r{{[0-9]+}}]!
|
||||
; A9: add.w r
|
||||
; A9-NOT: {{ldr|str|adds|add r}}
|
||||
; A9: add.w r
|
||||
; A9-NOT: {{ldr|str|adds|add r}}
|
||||
|
|
|
|||
Loading…
Reference in New Issue