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[mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node. 

Patch by Sasa Stankovic.

llvm-svn: 167548
This commit is contained in:
Akira Hatanaka 2012-11-07 19:10:58 +00:00
parent 0da2fa3561
commit 28e02ec8c1
3 changed files with 90 additions and 0 deletions
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26
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -247,6 +247,10 @@ MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
}
setOperationAction(ISD::ADD, MVT::i32, Custom);
if (HasMips64)
setOperationAction(ISD::ADD, MVT::i64, Custom);
setOperationAction(ISD::SDIV, MVT::i32, Expand);
setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::UDIV, MVT::i32, Expand);
@ -914,6 +918,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
case ISD::STORE: return LowerSTORE(Op, DAG);
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
case ISD::ADD: return LowerADD(Op, DAG);
}
return SDValue();
}
@ -2541,6 +2546,27 @@ SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
}
}
SDValue MipsTargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
|| cast<ConstantSDNode>
(Op->getOperand(0).getOperand(0))->getZExtValue() != 0
|| Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
return SDValue();
// The pattern
// (add (frameaddr 0), (frame_to_args_offset))
// results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
// (add FrameObject, 0)
// where FrameObject is a fixed StackObject with offset 0 which points to
// the old stack pointer.
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
EVT ValTy = Op->getValueType(0);
int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
return DAG.getNode(ISD::ADD, Op->getDebugLoc(), ValTy, InArgsAddr,
DAG.getConstant(0, ValTy));
}
//===----------------------------------------------------------------------===//
// Calling Convention Implementation
//===----------------------------------------------------------------------===//

1
llvm/lib/Target/Mips/MipsISelLowering.h
View File

@ -272,6 +272,7 @@ namespace llvm {
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
/// for tail call optimization.

63
llvm/test/CodeGen/Mips/eh-dwarf-cfa.ll Normal file
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@ -0,0 +1,63 @@
; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips64 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-MIPS64
declare i8* @llvm.eh.dwarf.cfa(i32) nounwind
declare i8* @llvm.frameaddress(i32) nounwind readnone
define i8* @f1() nounwind {
entry:
%x = alloca [32 x i8], align 1
%0 = call i8* @llvm.eh.dwarf.cfa(i32 0)
ret i8* %0
; CHECK: addiu $sp, $sp, -32
; CHECK: addiu $2, $sp, 32
}
define i8* @f2() nounwind {
entry:
%x = alloca [65536 x i8], align 1
%0 = call i8* @llvm.eh.dwarf.cfa(i32 0)
ret i8* %0
; check stack size (65536 + 8)
; CHECK: lui $[[R0:[a-z0-9]+]], 65535
; CHECK: addiu $[[R0]], $[[R0]], -8
; CHECK: addu $sp, $sp, $[[R0]]
; check return value ($sp + stack size)
; CHECK: lui $[[R1:[a-z0-9]+]], 1
; CHECK: addu $[[R1]], $sp, $[[R1]]
; CHECK: addiu $2, $[[R1]], 8
}
define i32 @f3() nounwind {
entry:
%x = alloca [32 x i8], align 1
%0 = call i8* @llvm.eh.dwarf.cfa(i32 0)
%1 = ptrtoint i8* %0 to i32
%2 = call i8* @llvm.frameaddress(i32 0)
%3 = ptrtoint i8* %2 to i32
%add = add i32 %1, %3
ret i32 %add
; CHECK: addiu $sp, $sp, -40
; check return value ($fp + stack size + $fp)
; CHECK: addiu $[[R0:[a-z0-9]+]], $fp, 40
; CHECK: addu $2, $[[R0]], $fp
}
define i8* @f4() nounwind {
entry:
%x = alloca [32 x i8], align 1
%0 = call i8* @llvm.eh.dwarf.cfa(i32 0)
ret i8* %0
; CHECK-MIPS64: daddiu $sp, $sp, -32
; CHECK-MIPS64: daddiu $2, $sp, 32
}