[SystemZ] Start adding z196 and zEC12 support
This first step just adds definitions for SLLK, SRLK and SRAK. The next patch will actually make use of them during codegen. insn-bad.s tests that some form of error is reported when using these instructions on z10. More work is needed to get the "instruction requires: distinct-ops" that we'd ideally like, so I've stubbed that part out for now. I'll come back and make it mandatory once the necessary changes are in. llvm-svn: 186680
This commit is contained in:
Richard Sandiford
parent
67080cec25
commit
27d1cfe3d4
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@ -14,13 +14,10 @@
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// SystemZ supported processors
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// SystemZ supported processors and features
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"z10", []>;
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include "SystemZProcessors.td"
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//===----------------------------------------------------------------------===//
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// Register file description
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@ -816,20 +816,27 @@ multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
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}
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class ShiftRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
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RegisterOperand cls, AddressingMode mode>
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: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
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RegisterOperand cls>
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: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
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mnemonic#"\t$R1, $BD2",
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[(set cls:$R1, (operator cls:$R1src, mode:$BD2))]> {
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[(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
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let R3 = 0;
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let Constraints = "$R1 = $R1src";
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let DisableEncoding = "$R1src";
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}
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class ShiftRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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RegisterOperand cls, AddressingMode mode>
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: InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
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RegisterOperand cls>
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: InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
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mnemonic#"\t$R1, $R3, $BD2",
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[(set cls:$R1, (operator cls:$R3, mode:$BD2))]>;
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[(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
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multiclass ShiftRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
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SDPatternOperator operator, RegisterOperand cls> {
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def K : ShiftRSY<mnemonic##"k", opcode2, null_frag, cls>,
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Requires<[FeatureDistinctOps]>;
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def "" : ShiftRS<mnemonic, opcode1, operator, cls>;
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}
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class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
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RegisterOperand cls1, RegisterOperand cls2>
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@ -796,26 +796,26 @@ def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>;
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// Shift left.
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let neverHasSideEffects = 1 in {
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def SLL : ShiftRS <"sll", 0x89, shl, GR32, shift12only>;
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def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64, shift20only>;
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defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
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def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>;
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}
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// Logical shift right.
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let neverHasSideEffects = 1 in {
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def SRL : ShiftRS <"srl", 0x88, srl, GR32, shift12only>;
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def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64, shift20only>;
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defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
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def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>;
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}
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// Arithmetic shift right.
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let Defs = [CC] in {
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def SRA : ShiftRS <"sra", 0x8A, sra, GR32, shift12only>;
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def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64, shift20only>;
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defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
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def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>;
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}
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// Rotate left.
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let neverHasSideEffects = 1 in {
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def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32, shift20only>;
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def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64, shift20only>;
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def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32>;
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def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>;
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}
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// Rotate second operand left and inserted selected bits into first operand.
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@ -0,0 +1,26 @@
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//===-- SystemZ.td - SystemZ processors and features ---------*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Processor and feature definitions.
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//
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//===----------------------------------------------------------------------===//
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class SystemZFeature<string extname, string intname, string desc>
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: Predicate<"Subtarget.has"##intname##"()">,
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AssemblerPredicate<"Feature"##intname, extname>,
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SubtargetFeature<extname, "Has"##intname, "true", desc>;
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def FeatureDistinctOps : SystemZFeature<
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"distinct-ops", "DistinctOps",
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"Assume that the distinct-operands facility is installed"
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>;
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def : Processor<"z10", NoItineraries, []>;
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def : Processor<"z196", NoItineraries, [FeatureDistinctOps]>;
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def : Processor<"zEC12", NoItineraries, [FeatureDistinctOps]>;
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@ -9,6 +9,7 @@
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#include "SystemZSubtarget.h"
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#include "llvm/IR/GlobalValue.h"
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#include "MCTargetDesc/SystemZMCTargetDesc.h"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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@ -19,7 +20,8 @@ using namespace llvm;
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SystemZSubtarget::SystemZSubtarget(const std::string &TT,
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const std::string &CPU,
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const std::string &FS)
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: SystemZGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT) {
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: SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
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TargetTriple(TT) {
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "z10";
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@ -26,6 +26,9 @@ class GlobalValue;
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class StringRef;
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class SystemZSubtarget : public SystemZGenSubtargetInfo {
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protected:
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bool HasDistinctOps;
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private:
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Triple TargetTriple;
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@ -36,6 +39,9 @@ public:
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// Automatically generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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// Return true if the target has the distinct-operands facility.
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bool hasDistinctOps() const { return HasDistinctOps; }
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// Return true if GV can be accessed using LARL for reloc model RM
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// and code model CM.
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bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,
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@ -1,5 +1,5 @@
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# Test instructions that don't have PC-relative operands.
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# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s
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# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
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# CHECK: adbr %f0, %f0
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0xb3 0x1a 0x00 0x00
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@ -5215,6 +5215,42 @@
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# CHECK: sllg %r0, %r0, 524287(%r15)
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0xeb 0x00 0xff 0xff 0x7f 0x0d
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# CHECK: sllk %r0, %r0, 0
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0xeb 0x00 0x00 0x00 0x00 0xdf
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# CHECK: sllk %r15, %r1, 0
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0xeb 0xf1 0x00 0x00 0x00 0xdf
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# CHECK: sllk %r1, %r15, 0
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0xeb 0x1f 0x00 0x00 0x00 0xdf
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# CHECK: sllk %r15, %r15, 0
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0xeb 0xff 0x00 0x00 0x00 0xdf
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# CHECK: sllk %r0, %r0, -524288
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0xeb 0x00 0x00 0x00 0x80 0xdf
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# CHECK: sllk %r0, %r0, -1
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0xeb 0x00 0x0f 0xff 0xff 0xdf
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# CHECK: sllk %r0, %r0, 1
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0xeb 0x00 0x00 0x01 0x00 0xdf
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# CHECK: sllk %r0, %r0, 524287
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0xeb 0x00 0x0f 0xff 0x7f 0xdf
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# CHECK: sllk %r0, %r0, 0(%r1)
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0xeb 0x00 0x10 0x00 0x00 0xdf
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# CHECK: sllk %r0, %r0, 0(%r15)
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0xeb 0x00 0xf0 0x00 0x00 0xdf
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# CHECK: sllk %r0, %r0, 524287(%r1)
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0xeb 0x00 0x1f 0xff 0x7f 0xdf
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# CHECK: sllk %r0, %r0, 524287(%r15)
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0xeb 0x00 0xff 0xff 0x7f 0xdf
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# CHECK: sll %r0, 0
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0x89 0x00 0x00 0x00
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@ -5416,6 +5452,42 @@
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# CHECK: srag %r0, %r0, 524287(%r15)
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0xeb 0x00 0xff 0xff 0x7f 0x0a
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# CHECK: srak %r0, %r0, 0
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0xeb 0x00 0x00 0x00 0x00 0xdc
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# CHECK: srak %r15, %r1, 0
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0xeb 0xf1 0x00 0x00 0x00 0xdc
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# CHECK: srak %r1, %r15, 0
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0xeb 0x1f 0x00 0x00 0x00 0xdc
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# CHECK: srak %r15, %r15, 0
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0xeb 0xff 0x00 0x00 0x00 0xdc
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# CHECK: srak %r0, %r0, -524288
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0xeb 0x00 0x00 0x00 0x80 0xdc
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# CHECK: srak %r0, %r0, -1
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0xeb 0x00 0x0f 0xff 0xff 0xdc
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# CHECK: srak %r0, %r0, 1
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0xeb 0x00 0x00 0x01 0x00 0xdc
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# CHECK: srak %r0, %r0, 524287
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0xeb 0x00 0x0f 0xff 0x7f 0xdc
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# CHECK: srak %r0, %r0, 0(%r1)
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0xeb 0x00 0x10 0x00 0x00 0xdc
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# CHECK: srak %r0, %r0, 0(%r15)
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0xeb 0x00 0xf0 0x00 0x00 0xdc
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# CHECK: srak %r0, %r0, 524287(%r1)
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0xeb 0x00 0x1f 0xff 0x7f 0xdc
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# CHECK: srak %r0, %r0, 524287(%r15)
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0xeb 0x00 0xff 0xff 0x7f 0xdc
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# CHECK: sra %r0, 0
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0x8a 0x00 0x00 0x00
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@ -5476,6 +5548,42 @@
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# CHECK: srlg %r0, %r0, 524287(%r15)
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0xeb 0x00 0xff 0xff 0x7f 0x0c
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# CHECK: srlk %r0, %r0, 0
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0xeb 0x00 0x00 0x00 0x00 0xde
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# CHECK: srlk %r15, %r1, 0
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0xeb 0xf1 0x00 0x00 0x00 0xde
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# CHECK: srlk %r1, %r15, 0
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0xeb 0x1f 0x00 0x00 0x00 0xde
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# CHECK: srlk %r15, %r15, 0
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0xeb 0xff 0x00 0x00 0x00 0xde
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# CHECK: srlk %r0, %r0, -524288
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0xeb 0x00 0x00 0x00 0x80 0xde
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# CHECK: srlk %r0, %r0, -1
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0xeb 0x00 0x0f 0xff 0xff 0xde
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# CHECK: srlk %r0, %r0, 1
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0xeb 0x00 0x00 0x01 0x00 0xde
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# CHECK: srlk %r0, %r0, 524287
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0xeb 0x00 0x0f 0xff 0x7f 0xde
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# CHECK: srlk %r0, %r0, 0(%r1)
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0xeb 0x00 0x10 0x00 0x00 0xde
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# CHECK: srlk %r0, %r0, 0(%r15)
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0xeb 0x00 0xf0 0x00 0x00 0xde
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# CHECK: srlk %r0, %r0, 524287(%r1)
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0xeb 0x00 0x1f 0xff 0x7f 0xde
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# CHECK: srlk %r0, %r0, 524287(%r15)
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0xeb 0x00 0xff 0xff 0x7f 0xde
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# CHECK: srl %r0, 0
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0x88 0x00 0x00 0x00
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@ -0,0 +1,44 @@
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# For z196 only.
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# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=z196 < %s 2> %t
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# RUN: FileCheck < %t %s
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#CHECK: error: invalid operand
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#CHECK: sllk %r0,%r0,-524289
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#CHECK: error: invalid operand
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#CHECK: sllk %r0,%r0,524288
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#CHECK: error: %r0 used in an address
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#CHECK: sllk %r0,%r0,0(%r0)
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#CHECK: error: invalid use of indexed addressing
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#CHECK: sllk %r0,%r0,0(%r1,%r2)
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sllk %r0,%r0,-524289
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sllk %r0,%r0,524288
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sllk %r0,%r0,0(%r0)
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sllk %r0,%r0,0(%r1,%r2)
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#CHECK: error: invalid operand
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#CHECK: srak %r0,%r0,-524289
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#CHECK: error: invalid operand
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#CHECK: srak %r0,%r0,524288
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#CHECK: error: %r0 used in an address
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#CHECK: srak %r0,%r0,0(%r0)
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#CHECK: error: invalid use of indexed addressing
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#CHECK: srak %r0,%r0,0(%r1,%r2)
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srak %r0,%r0,-524289
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srak %r0,%r0,524288
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srak %r0,%r0,0(%r0)
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srak %r0,%r0,0(%r1,%r2)
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#CHECK: error: invalid operand
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#CHECK: srlk %r0,%r0,-524289
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#CHECK: error: invalid operand
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#CHECK: srlk %r0,%r0,524288
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#CHECK: error: %r0 used in an address
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#CHECK: srlk %r0,%r0,0(%r0)
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#CHECK: error: invalid use of indexed addressing
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#CHECK: srlk %r0,%r0,0(%r1,%r2)
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srlk %r0,%r0,-524289
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srlk %r0,%r0,524288
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srlk %r0,%r0,0(%r0)
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srlk %r0,%r0,0(%r1,%r2)
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@ -1,4 +1,5 @@
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# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t
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# For z10 only.
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# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=z10 < %s 2> %t
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# RUN: FileCheck < %t %s
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#CHECK: error: invalid operand
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@ -2343,6 +2344,11 @@
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sllg %r0,%r0,0(%r0)
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sllg %r0,%r0,0(%r1,%r2)
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#CHECK: error: {{(instruction requires: distinct-ops)?}}
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#CHECK: sllk %r2,%r3,4(%r5)
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sllk %r2,%r3,4(%r5)
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#CHECK: error: invalid operand
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#CHECK: sly %r0, -524289
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#CHECK: error: invalid operand
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@ -2403,6 +2409,11 @@
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srag %r0,%r0,0(%r0)
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srag %r0,%r0,0(%r1,%r2)
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#CHECK: error: {{(instruction requires: distinct-ops)?}}
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#CHECK: srak %r2,%r3,4(%r5)
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srak %r2,%r3,4(%r5)
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#CHECK: error: invalid operand
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#CHECK: srl %r0,-1
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#CHECK: error: invalid operand
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@ -2431,6 +2442,11 @@
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srlg %r0,%r0,0(%r0)
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srlg %r0,%r0,0(%r1,%r2)
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#CHECK: error: {{(instruction requires: distinct-ops)?}}
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#CHECK: srlk %r2,%r3,4(%r5)
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srlk %r2,%r3,4(%r5)
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#CHECK: error: invalid operand
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#CHECK: st %r0, -1
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#CHECK: error: invalid operand
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@ -0,0 +1,80 @@
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# For z196 and above.
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# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z196 -show-encoding %s | FileCheck %s
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#CHECK: sllk %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xdf]
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#CHECK: sllk %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xdf]
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#CHECK: sllk %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xdf]
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#CHECK: sllk %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0xdf]
|
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#CHECK: sllk %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0xdf]
|
||||
#CHECK: sllk %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0xdf]
|
||||
#CHECK: sllk %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0xdf]
|
||||
#CHECK: sllk %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xdf]
|
||||
#CHECK: sllk %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0xdf]
|
||||
#CHECK: sllk %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xdf]
|
||||
#CHECK: sllk %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0xdf]
|
||||
#CHECK: sllk %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0xdf]
|
||||
|
||||
sllk %r0,%r0,0
|
||||
sllk %r15,%r1,0
|
||||
sllk %r1,%r15,0
|
||||
sllk %r15,%r15,0
|
||||
sllk %r0,%r0,-524288
|
||||
sllk %r0,%r0,-1
|
||||
sllk %r0,%r0,1
|
||||
sllk %r0,%r0,524287
|
||||
sllk %r0,%r0,0(%r1)
|
||||
sllk %r0,%r0,0(%r15)
|
||||
sllk %r0,%r0,524287(%r1)
|
||||
sllk %r0,%r0,524287(%r15)
|
||||
|
||||
#CHECK: srak %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xdc]
|
||||
#CHECK: srak %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xdc]
|
||||
#CHECK: srak %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xdc]
|
||||
#CHECK: srak %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0xdc]
|
||||
#CHECK: srak %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0xdc]
|
||||
#CHECK: srak %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0xdc]
|
||||
#CHECK: srak %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0xdc]
|
||||
#CHECK: srak %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xdc]
|
||||
#CHECK: srak %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0xdc]
|
||||
#CHECK: srak %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xdc]
|
||||
#CHECK: srak %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0xdc]
|
||||
#CHECK: srak %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0xdc]
|
||||
|
||||
srak %r0,%r0,0
|
||||
srak %r15,%r1,0
|
||||
srak %r1,%r15,0
|
||||
srak %r15,%r15,0
|
||||
srak %r0,%r0,-524288
|
||||
srak %r0,%r0,-1
|
||||
srak %r0,%r0,1
|
||||
srak %r0,%r0,524287
|
||||
srak %r0,%r0,0(%r1)
|
||||
srak %r0,%r0,0(%r15)
|
||||
srak %r0,%r0,524287(%r1)
|
||||
srak %r0,%r0,524287(%r15)
|
||||
|
||||
#CHECK: srlk %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xde]
|
||||
#CHECK: srlk %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xde]
|
||||
#CHECK: srlk %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xde]
|
||||
#CHECK: srlk %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0xde]
|
||||
#CHECK: srlk %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0xde]
|
||||
#CHECK: srlk %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0xde]
|
||||
#CHECK: srlk %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0xde]
|
||||
#CHECK: srlk %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xde]
|
||||
#CHECK: srlk %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0xde]
|
||||
#CHECK: srlk %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xde]
|
||||
#CHECK: srlk %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0xde]
|
||||
#CHECK: srlk %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0xde]
|
||||
|
||||
srlk %r0,%r0,0
|
||||
srlk %r15,%r1,0
|
||||
srlk %r1,%r15,0
|
||||
srlk %r15,%r15,0
|
||||
srlk %r0,%r0,-524288
|
||||
srlk %r0,%r0,-1
|
||||
srlk %r0,%r0,1
|
||||
srlk %r0,%r0,524287
|
||||
srlk %r0,%r0,0(%r1)
|
||||
srlk %r0,%r0,0(%r15)
|
||||
srlk %r0,%r0,524287(%r1)
|
||||
srlk %r0,%r0,524287(%r15)
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
# For z10 and above.
|
||||
# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s
|
||||
|
||||
#CHECK: a %r0, 0 # encoding: [0x5a,0x00,0x00,0x00]
|
||||
|
|
|
|||
Loading…
Reference in New Issue