[X86] Split off PHMINPOSUW to their own schedule class
This also fixes Jaguar's schedule which was treating it as the WriteVecIMul default. llvm-svn: 330756
This commit is contained in:
Simon Pilgrim
parent
8a475307bd
commit
27bc83e228
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@ -5751,10 +5751,10 @@ multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
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let Predicates = [HasAVX] in
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defm VPHMINPOSUW : SS41I_unop_rm_int_v16<0x41, "vphminposuw",
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X86phminpos, loadv2i64,
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WriteVecIMul>, VEX, VEX_WIG;
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WritePHMINPOS>, VEX, VEX_WIG;
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defm PHMINPOSUW : SS41I_unop_rm_int_v16<0x41, "phminposuw",
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X86phminpos, memopv2i64,
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WriteVecIMul>;
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WritePHMINPOS>;
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/// SS48I_binop_rm - Simple SSE41 binary operator.
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multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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@ -194,7 +194,8 @@ defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1>; // Vector variable shuffl
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defm : BWWriteResPair<WriteBlend, [BWPort5], 1>; // Vector blends.
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defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2], 2, 5>; // Vector variable blends.
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defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD.
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defm : BWWriteResPair<WritePSADBW, [BWPort0], 5>; // Vector PSADBW.
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defm : BWWriteResPair<WritePSADBW, [BWPort0], 5>; // Vector PSADBW.
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defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS.
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// Vector insert/extract operations.
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def : WriteRes<WriteVecInsert, [BWPort5]> {
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@ -194,6 +194,7 @@ defm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2], 2, 6>;
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defm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 2, [2, 1]>;
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defm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 7, [1, 2], 3, 6>;
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defm : HWWriteResPair<WritePSADBW, [HWPort0], 5>;
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defm : HWWriteResPair<WritePHMINPOS, [HWPort0], 5, [1], 1, 6>;
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// Vector insert/extract operations.
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def : WriteRes<WriteVecInsert, [HWPort5]> {
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@ -1890,7 +1891,6 @@ def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> {
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let ResourceCycles = [1,1];
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}
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def: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm",
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"(V?)PHMINPOSUWrm",
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"(V?)PMADDUBSWrm",
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"(V?)PMADDWDrm",
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"(V?)PMULDQrm",
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@ -173,6 +173,7 @@ defm : SBWriteResPair<WriteBlend, [SBPort15], 1, [1], 1, 6>;
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defm : SBWriteResPair<WriteVarBlend, [SBPort15], 2, [2], 2, 6>;
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defm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 7, [1,2], 3, 6>;
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defm : SBWriteResPair<WritePSADBW, [SBPort0], 5>;
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defm : SBWriteResPair<WritePHMINPOS, [SBPort0], 5, [1], 1, 6>;
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// Vector insert/extract operations.
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def : WriteRes<WriteVecInsert, [SBPort5,SBPort15]> {
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@ -1537,8 +1538,7 @@ def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> {
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let NumMicroOps = 2;
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let ResourceCycles = [1,1];
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}
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def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm",
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"(V?)PHMINPOSUWrm")>;
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def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>;
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def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> {
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let Latency = 11;
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@ -192,6 +192,7 @@ defm : SKLWriteResPair<WriteBlend, [SKLPort5], 1, [1], 1, 6>; // Vector blends.
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defm : SKLWriteResPair<WriteVarBlend, [SKLPort015], 2, [2], 2, 6>; // Vector variable blends.
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defm : SKLWriteResPair<WriteMPSAD, [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD.
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defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3>; // Vector PSADBW.
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defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS.
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// Vector insert/extract operations.
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def : WriteRes<WriteVecInsert, [SKLPort5]> {
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@ -927,7 +928,6 @@ def: InstRW<[SKLWriteResGroup48], (instregex "(V?)ADDPD(Y?)rr",
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"(V?)MULPS(Y?)rr",
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"(V?)MULSDrr",
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"(V?)MULSSrr",
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"(V?)PHMINPOSUWrr",
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"(V?)PMADDUBSW(Y?)rr",
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"(V?)PMADDWD(Y?)rr",
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"(V?)PMULDQ(Y?)rr",
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@ -1883,7 +1883,6 @@ def: InstRW<[SKLWriteResGroup134], (instregex "(V?)ADDPDrm",
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"(V?)CVTTPS2DQrm",
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"(V?)MULPDrm",
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"(V?)MULPSrm",
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"(V?)PHMINPOSUWrm",
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"(V?)PMADDUBSWrm",
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"(V?)PMADDWDrm",
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"(V?)PMULDQrm",
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@ -192,6 +192,7 @@ defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends.
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defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends.
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defm : SKXWriteResPair<WriteMPSAD, [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD.
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defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3, [1,1], 1, 6>; // Vector PSADBW.
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defm : SKXWriteResPair<WritePHMINPOS, [SKXPort015], 4, [1], 1, 6>; // Vector PHMINPOS.
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// Vector insert/extract operations.
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def : WriteRes<WriteVecInsert, [SKXPort5]> {
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@ -1615,7 +1616,6 @@ def: InstRW<[SKXWriteResGroup50], (instregex "ADDPDrr",
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"MULPSrr",
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"MULSDrr",
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"MULSSrr",
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"PHMINPOSUWrr",
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"PMADDUBSWrr",
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"PMADDWDrr",
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"PMULDQrr",
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@ -1726,7 +1726,6 @@ def: InstRW<[SKXWriteResGroup50], (instregex "ADDPDrr",
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"VMULSDrr",
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"VMULSSZrr",
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"VMULSSrr",
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"VPHMINPOSUWrr",
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"VPLZCNTDZ128rr",
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"VPLZCNTDZ256rr",
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"VPLZCNTDZrr",
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@ -3893,7 +3892,6 @@ def: InstRW<[SKXWriteResGroup149], (instregex "ADDPDrm",
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"CVTTPS2DQrm",
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"MULPDrm",
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"MULPSrm",
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"PHMINPOSUWrm",
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"PMADDUBSWrm",
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"PMADDWDrm",
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"PMULDQrm",
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@ -3958,7 +3956,6 @@ def: InstRW<[SKXWriteResGroup149], (instregex "ADDPDrm",
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"VMULPSrm",
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"VMULSDZrm",
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"VMULSSZrm",
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"VPHMINPOSUWrm",
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"VPLZCNTDZ128rm(b?)",
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"VPLZCNTQZ128rm(b?)",
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"VPMADDUBSWZ128rm(b?)",
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@ -116,6 +116,7 @@ defm WriteBlend : X86SchedWritePair; // Vector blends.
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defm WriteVarBlend : X86SchedWritePair; // Vector variable blends.
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defm WritePSADBW : X86SchedWritePair; // Vector PSADBW.
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defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD.
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defm WritePHMINPOS : X86SchedWritePair; // Vector PHMINPOS.
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// Vector insert/extract operations.
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defm WriteVecInsert : X86SchedWritePair; // Insert gpr to vector element.
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@ -242,6 +242,7 @@ defm : AtomWriteResPair<WriteVecLogic, [AtomPort01], [AtomPort0], 1, 1>;
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defm : AtomWriteResPair<WriteVecShift, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>;
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defm : AtomWriteResPair<WriteVecIMul, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
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defm : AtomWriteResPair<WritePMULLD, [AtomPort01], [AtomPort0], 1, 1>;
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defm : AtomWriteResPair<WritePHMINPOS, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
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defm : AtomWriteResPair<WriteMPSAD, [AtomPort01], [AtomPort0], 1, 1>;
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defm : AtomWriteResPair<WritePSADBW, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
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defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>;
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@ -376,6 +376,7 @@ defm : JWriteResFpuPair<WriteVecIMul, [JFPU0, JVIMUL], 2>;
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defm : JWriteResFpuPair<WritePMULLD, [JFPU0, JFPU01, JVIMUL, JVALU], 4, [2, 1, 2, 1], 3>;
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defm : JWriteResFpuPair<WriteMPSAD, [JFPU0, JVIMUL], 3, [1, 2]>;
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defm : JWriteResFpuPair<WritePSADBW, [JFPU01, JVALU], 2>;
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defm : JWriteResFpuPair<WritePHMINPOS, [JFPU0, JVALU], 2>;
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defm : JWriteResFpuPair<WriteShuffle, [JFPU01, JVALU], 1>;
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defm : JWriteResFpuPair<WriteVarShuffle, [JFPU01, JVALU], 2, [1, 4], 3>;
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defm : JWriteResFpuPair<WriteBlend, [JFPU01, JVALU], 1>;
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@ -164,6 +164,7 @@ defm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7>;
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defm : SLMWriteResPair<WritePSADBW, [SLM_FPC_RSV0], 4>;
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defm : SLMWriteResPair<WritePHMINPOS, [SLM_FPC_RSV0], 4>;
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// Vector insert/extract operations.
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defm : SLMWriteResPair<WriteVecInsert, [SLM_FPC_RSV0], 1>;
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@ -230,6 +230,7 @@ defm : ZnWriteResFpuPair<WriteBlend, [ZnFPU01], 1>;
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defm : ZnWriteResFpuPair<WriteShuffle256, [ZnFPU], 2>;
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defm : ZnWriteResFpuPair<WriteVarShuffle256, [ZnFPU], 2>;
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defm : ZnWriteResFpuPair<WritePSADBW, [ZnFPU0], 3>;
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defm : ZnWriteResFpuPair<WritePHMINPOS, [ZnFPU0], 4>;
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// Vector Shift Operations
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defm : ZnWriteResFpuPair<WriteVarVecShift, [ZnFPU12], 1>;
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@ -1720,7 +1720,7 @@ vzeroupper
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
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# CHECK-NEXT: 48.00 2.00 - 355.50 907.50 402.00 398.00 381.00 - 43.00 114.00 116.50 116.50 40.00
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# CHECK-NEXT: 48.00 2.00 - 355.50 907.50 402.00 398.00 381.00 - 43.00 114.00 117.50 117.50 38.00
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
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@ -2147,8 +2147,8 @@ vzeroupper
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# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - vphaddsw (%rax), %xmm1, %xmm2
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vphaddw %xmm0, %xmm1, %xmm2
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# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - vphaddw (%rax), %xmm1, %xmm2
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# CHECK-NEXT: - - - - - 1.00 - - - - - - - 1.00 vphminposuw %xmm0, %xmm2
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# CHECK-NEXT: - - - - - 1.00 - 1.00 - - - - - 1.00 vphminposuw (%rax), %xmm2
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# CHECK-NEXT: - - - - - 1.00 - - - - - 0.50 0.50 - vphminposuw %xmm0, %xmm2
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# CHECK-NEXT: - - - - - 1.00 - 1.00 - - - 0.50 0.50 - vphminposuw (%rax), %xmm2
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vphsubd %xmm0, %xmm1, %xmm2
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# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - vphsubd (%rax), %xmm1, %xmm2
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vphsubsw %xmm0, %xmm1, %xmm2
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@ -270,7 +270,7 @@ roundss $1, (%rax), %xmm2
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
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# CHECK-NEXT: 6.00 - - 37.00 23.00 57.50 42.50 44.00 - 5.00 5.00 31.50 31.50 12.00
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# CHECK-NEXT: 6.00 - - 37.00 23.00 57.50 42.50 44.00 - 5.00 5.00 32.50 32.50 10.00
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
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@ -308,8 +308,8 @@ roundss $1, (%rax), %xmm2
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# CHECK-NEXT: 1.00 - - 1.00 - 1.00 - - - - - - - - pextrq $1, %xmm0, %rcx
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# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - pextrq $1, %xmm0, (%rax)
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# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - pextrw $1, %xmm0, (%rax)
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# CHECK-NEXT: - - - - - 1.00 - - - - - - - 1.00 phminposuw %xmm0, %xmm2
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# CHECK-NEXT: - - - - - 1.00 - 1.00 - - - - - 1.00 phminposuw (%rax), %xmm2
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# CHECK-NEXT: - - - - - 1.00 - - - - - 0.50 0.50 - phminposuw %xmm0, %xmm2
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# CHECK-NEXT: - - - - - 1.00 - 1.00 - - - 0.50 0.50 - phminposuw (%rax), %xmm2
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - pinsrb $1, %eax, %xmm1
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# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - pinsrb $1, (%rax), %xmm1
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - pinsrd $1, %eax, %xmm1
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