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ARM push of a single register encodes as pre-indexed STR. 

Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
This commit is contained in:
Jim Grosbach 2011-08-11 18:07:11 +00:00
parent 266ab10012
commit 27ad83d8a9
4 changed files with 25 additions and 3 deletions
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16
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -2879,6 +2879,22 @@ processInstruction(MCInst &Inst,
Inst = TmpInst;
}
break;
case ARM::STMDB_UPD:
// If this is a store of a single register via a 'push', then we should use
// a pre-indexed STR instruction instead, per the ARM ARM.
if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
Inst.getNumOperands() == 5) {
MCInst TmpInst;
TmpInst.setOpcode(ARM::STR_PRE_IMM);
TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(4)); // Rt
TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
TmpInst.addOperand(MCOperand::CreateImm(-4));
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
}
break;
}
}

7
llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -88,6 +88,13 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
printRegisterList(MI, 4, O);
return;
}
if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
MI->getOperand(3).getImm() == -4) {
O << '\t' << "push";
printPredicateOperand(MI, 4, O);
O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
return;
}
// A8.6.122 POP
if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&

2
llvm/test/CodeGen/ARM/str_pre-2.ll
View File

@ -7,7 +7,7 @@
define i64 @t(i64 %a) nounwind readonly {
entry:
; CHECK: str lr, [sp, #-4]!
; CHECK: push {lr}
; CHECK: pop {lr}
%0 = load i64** @b, align 4
%1 = load i64* %0, align 4

3
llvm/test/MC/ARM/basic-arm-instructions.s
View File

@ -1071,8 +1071,7 @@ Lforward:
push {r7}
push {r7, r8, r9, r10}
@ FIXME: push of a single register should encode as "str r7, [sp, #-4]!"
@ CHECK-FIXME: push {r7} @ encoding: [0x04,0x70,0x2d,0xe5]
@ CHECK: push {r7} @ encoding: [0x04,0x70,0x2d,0xe5]
@ CHECK: push {r7, r8, r9, r10} @ encoding: [0x80,0x07,0x2d,0xe9]