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remove a pseudo instruction and improve inline constant generation 

llvm-svn: 20563
This commit is contained in:
Andrew Lenharth 2005-03-11 17:48:05 +00:00
parent db302f899a
commit 27a3df07a0
2 changed files with 29 additions and 6 deletions
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32
llvm/lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -326,6 +326,25 @@ public:
};
}
//These describe LDAx
static const int64_t IMM_LOW = 0xffffffffffff8000LL;
static const int IMM_HIGH = 0x0000000000007fffLL;
static const int IMM_MULT = 65536;
static long getUpper16(long l)
{
long y = l / IMM_MULT;
if (l % IMM_MULT > IMM_HIGH)
++y;
return y;
}
static long getLower16(long l)
{
long h = getUpper16(l);
return l - h * IMM_MULT;
}
static unsigned GetSymVersion(unsigned opcode)
{
switch (opcode) {
@ -1447,9 +1466,16 @@ unsigned ISel::SelectExpr(SDOperand N) {
case ISD::Constant:
{
unsigned long val = cast<ConstantSDNode>(N)->getValue();
if (val < 32000 && (long)val > -32000)
BuildMI(BB, Alpha::LOAD_IMM, 1, Result).addImm((long)val);
int64_t val = (long)cast<ConstantSDNode>(N)->getValue();
if (val <= IMM_HIGH && val >= IMM_LOW) {
BuildMI(BB, Alpha::LDA, 2, Result).addImm(val).addReg(Alpha::R31);
}
else if (val <= (int64_t)IMM_HIGH + (int64_t)IMM_HIGH * (int64_t)IMM_MULT &&
val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
Tmp1 = MakeReg(MVT::i64);
BuildMI(BB, Alpha::LDAH, 2, Tmp1).addImm(getUpper16(val)).addReg(Alpha::R31);
BuildMI(BB, Alpha::LDA, 2, Result).addImm(getLower16(val)).addReg(Tmp1);
}
else {
MachineConstantPool *CP = BB->getParent()->getConstantPool();
ConstantUInt *C = ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);

3
llvm/lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -53,9 +53,6 @@ let isCall = 1,
let isReturn = 1, isTerminator = 1 in
def RETURN : PseudoInstAlpha<(ops ), "ret $$31,($$26),1">; //Return from subroutine
let Uses = [R29], Defs = [R28] in
def LOAD_IMM : PseudoInstAlpha<(ops GPRC:$RC, s64imm:$IMM), "ldiq $RC,$IMM">; //Load Immediate Quadword
let Uses = [R29], Defs = [R28] in {
def LOAD_ADDR : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lda $RA,$DISP">; //Load address
def LDQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword