From 279cabb4504635df2afa7e28e714f6894a190f9b Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Sun, 25 Jan 2015 18:05:42 +0000 Subject: [PATCH] [PowerPC] Reset the baseline for ppc64le to be equivalent to pwr8 Test by Nemanja Ivanovic. Since ppc64le implies POWER8 as a minimum, it makes sense that the same features are included. Since the pwr8 processor model will likely be getting new features until the implementation is complete, I created a new list to add these updates to. This will include them in both pwr8 and ppc64le. Furthermore, it seems that it would make sense to compose the feature lists for other processor models (pwr3 and up). Per discussion in the review, I will make this change in a subsequent patch. In order to test the changes, I've added an additional run step to test cases that specify -march=ppc64le -mcpu=pwr8 to omit the -mcpu option. Since the feature lists are the same, the behaviour should be unchanged. llvm-svn: 227053 --- llvm/lib/Target/PowerPC/PPC.td | 44 +++++++++++++------ .../CodeGen/PowerPC/ppc64le-aggregates.ll | 3 ++ llvm/test/CodeGen/PowerPC/ppc64le-calls.ll | 4 ++ .../CodeGen/PowerPC/ppc64le-localentry.ll | 5 +++ 4 files changed, 42 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index c94a64885409..bd16c67a5862 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -242,6 +242,34 @@ def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, FeatureFRES, FeatureFRSQRTE]>; def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, FeatureFRES, FeatureFRSQRTE]>; + +/* Since new processors generally contain a superset of features of those that + came before them, the idea is to make implementations of new processors + less error prone and easier to read. + Namely: + list Power8FeatureList = ... + list FutureProcessorSpecificFeatureList = + [ features that Power8 does not support ] + list FutureProcessorFeatureList = + !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList) + + Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as + well as providing a single point of definition if the feature set will be + used elsewhere. + +*/ +def ProcessorFeatures { + list Power8FeatureList = + [DirectivePwr8, FeatureAltivec, FeatureVSX, FeatureP8Vector, + FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, + FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, + FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, + FeatureFPRND, FeatureFPCVT, FeatureISEL, + FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, + Feature64Bit /*, Feature64BitRegs */, FeatureICBT, + DeprecatedMFTB, DeprecatedDST]; +} + def : ProcessorModel<"970", G5Model, [Directive970, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, @@ -320,26 +348,14 @@ def : ProcessorModel<"pwr7", P7Model, FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */, DeprecatedMFTB, DeprecatedDST]>; -def : ProcessorModel<"pwr8", P8Model, - [DirectivePwr8, FeatureAltivec, FeatureVSX, FeatureP8Vector, - FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, - FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, - FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, - FeatureFPRND, FeatureFPCVT, FeatureISEL, - FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, - Feature64Bit /*, Feature64BitRegs */, FeatureICBT, - DeprecatedMFTB, DeprecatedDST]>; +def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>; def : Processor<"ppc", G3Itineraries, [Directive32]>; def : ProcessorModel<"ppc64", G5Model, [Directive64, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */]>; -def : ProcessorModel<"ppc64le", G5Model, - [Directive64, FeatureAltivec, - FeatureMFOCRF, FeatureFSqrt, FeatureFRES, - FeatureFRSQRTE, FeatureSTFIWX, - Feature64Bit /*, Feature64BitRegs */]>; +def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>; //===----------------------------------------------------------------------===// // Calling Conventions diff --git a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll index 4edd8d59e526..7c82d72a2799 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll @@ -1,8 +1,11 @@ ; RUN: llc < %s -march=ppc64le -mcpu=pwr8 -mattr=+altivec -mattr=-vsx | FileCheck %s +; RUN: llc < %s -march=ppc64le -mattr=+altivec -mattr=-vsx | FileCheck %s ; Currently VSX support is disabled for this test because we generate lxsdx ; instead of lfd, and stxsdx instead of stfd. That is a poor choice when we ; have reg+imm addressing, and is on the list of things to be fixed. +; The second run of the test case is to ensure the behaviour is the same +; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le. target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/ppc64le-calls.ll b/llvm/test/CodeGen/PowerPC/ppc64le-calls.ll index 0d667dde96b4..b65b9549b6b1 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64le-calls.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64le-calls.ll @@ -1,4 +1,8 @@ ; RUN: llc -march=ppc64le -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -march=ppc64le < %s | FileCheck %s + +; The second run of the test case is to ensure the behaviour is the same +; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le. target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/ppc64le-localentry.ll b/llvm/test/CodeGen/PowerPC/ppc64le-localentry.ll index 4676ce8eadc6..d9995de9b727 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64le-localentry.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64le-localentry.ll @@ -1,5 +1,10 @@ ; RUN: llc -march=ppc64le -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -march=ppc64le -mcpu=pwr8 -O0 < %s | FileCheck %s +; RUN: llc -march=ppc64le < %s | FileCheck %s +; RUN: llc -march=ppc64le -O0 < %s | FileCheck %s + +; The second run of the test case is to ensure the behaviour is the same +; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le. target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu"