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Give TargetRegisterClass a pointer to the MCRegisterClass and use it to access its data. 

This makes TargetRegisterClass slightly slower. Next step will be making contains faster.
Eventually TargetRegisterClass will be killed entirely.

llvm-svn: 135835
This commit is contained in:
Benjamin Kramer 2011-07-23 00:47:46 +00:00
parent 06e70d33fc
commit 2754ca1e10
2 changed files with 77 additions and 42 deletions
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69
llvm/include/llvm/Target/TargetRegisterInfo.h
View File

@ -32,32 +32,81 @@ class RegScavenger;
template<class T> class SmallVectorImpl;
class raw_ostream;
class TargetRegisterClass : public MCRegisterClass {
class TargetRegisterClass {
public:
typedef const unsigned* iterator;
typedef const unsigned* const_iterator;
typedef const EVT* vt_iterator;
typedef const TargetRegisterClass* const * sc_iterator;
private:
const MCRegisterClass *MC;
const vt_iterator VTs;
const sc_iterator SubClasses;
const sc_iterator SuperClasses;
const sc_iterator SubRegClasses;
const sc_iterator SuperRegClasses;
public:
TargetRegisterClass(unsigned id, const char *name, const EVT *vts,
TargetRegisterClass(MCRegisterClass *MC, const EVT *vts,
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
const TargetRegisterClass * const *subregcs,
const TargetRegisterClass * const *superregcs,
unsigned RS, unsigned Al, int CC, bool Allocable,
iterator RB, iterator RE)
: MCRegisterClass(id, name, RS, Al, CC, Allocable, RB, RE),
VTs(vts), SubClasses(subcs), SuperClasses(supcs), SubRegClasses(subregcs),
SuperRegClasses(superregcs) {
initMCRegisterClass();
}
const TargetRegisterClass * const *superregcs)
: MC(MC), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
SubRegClasses(subregcs), SuperRegClasses(superregcs) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
/// getID() - Return the register class ID number.
///
unsigned getID() const { return MC->getID(); }
/// getName() - Return the register class name for debugging.
///
const char *getName() const { return MC->getName(); }
/// begin/end - Return all of the registers in this class.
///
iterator begin() const { return MC->begin(); }
iterator end() const { return MC->end(); }
/// getNumRegs - Return the number of registers in this class.
///
unsigned getNumRegs() const { return MC->getNumRegs(); }
/// getRegister - Return the specified register in the class.
///
unsigned getRegister(unsigned i) const {
return MC->getRegister(i);
}
/// contains - Return true if the specified register is included in this
/// register class. This does not include virtual registers.
bool contains(unsigned Reg) const {
return MC->contains(Reg);
}
/// contains - Return true if both registers are in this class.
bool contains(unsigned Reg1, unsigned Reg2) const {
return MC->contains(Reg1, Reg2);
}
/// getSize - Return the size of the register in bytes, which is also the size
/// of a stack slot allocated to hold a spilled copy of this register.
unsigned getSize() const { return MC->getSize(); }
/// getAlignment - Return the minimum required alignment for a register of
/// this class.
unsigned getAlignment() const { return MC->getAlignment(); }
/// getCopyCost - Return the cost of copying a value between two registers in
/// this class. A negative number means the register class is very expensive
/// to copy e.g. status flag register classes.
int getCopyCost() const { return MC->getCopyCost(); }
/// isAllocatable - Return true if this register class may be used to create
/// virtual registers.
bool isAllocatable() const { return MC->isAllocatable(); }
/// hasType - return true if this TargetRegisterClass has the ValueType vt.
///
bool hasType(EVT vt) const {

50
llvm/utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -297,7 +297,6 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
}
OS << "};\n\n"; // End of register descriptors...
// FIXME: This code is duplicated in the TargetRegisterClass emitter.
const std::vector<CodeGenRegisterClass> &RegisterClasses =
Target.getRegisterClasses();
@ -446,6 +445,10 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << "namespace llvm {\n\n";
// Get access to MCRegisterClass data.
OS << "extern MCRegisterClass " << Target.getName()
<< "MCRegisterClasses[];\n";
// Start out by emitting each of the register classes.
const std::vector<CodeGenRegisterClass> &RegisterClasses =
Target.getRegisterClasses();
@ -453,32 +456,17 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Collect all registers belonging to any allocatable class.
std::set<Record*> AllocatableRegs;
// Loop over all of the register classes... emitting each one.
OS << "namespace { // Register classes...\n";
// Emit the register enum value arrays for each RegisterClass
// Collect allocatable registers.
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
ArrayRef<Record*> Order = RC.getOrder();
// Collect allocatable registers.
if (RC.Allocatable)
AllocatableRegs.insert(Order.begin(), Order.end());
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.getName();
// Emit the register list now.
OS << " // " << Name << " Register Class...\n"
<< " static const unsigned " << Name
<< "[] = {\n ";
for (unsigned i = 0, e = Order.size(); i != e; ++i) {
Record *Reg = Order[i];
OS << getQualifiedName(Reg) << ", ";
}
OS << "\n };\n\n";
}
OS << "namespace { // Register classes...\n";
// Emit the ValueType arrays for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
@ -656,22 +644,16 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
const CodeGenRegisterClass &RC = RegisterClasses[i];
OS << RC.getName() << "Class::" << RC.getName()
<< "Class() : TargetRegisterClass("
<< RC.getName() + "RegClassID" << ", "
<< '\"' << RC.getName() << "\", "
<< "Class() : TargetRegisterClass(&"
<< Target.getName() << "MCRegisterClasses["
<< RC.getName() + "RegClassID" << "], "
<< RC.getName() + "VTs" << ", "
<< RC.getName() + "Subclasses" << ", "
<< RC.getName() + "Superclasses" << ", "
<< (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
<< "RegClasses, "
<< (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
<< "RegClasses, "
<< RC.SpillSize/8 << ", "
<< RC.SpillAlignment/8 << ", "
<< RC.CopyCost << ", "
<< RC.Allocatable << ", "
<< RC.getName() << ", " << RC.getName() << " + "
<< RC.getOrder().size()
<< "RegClasses"
<< ") {}\n";
if (!RC.AltOrderSelect.empty()) {
OS << "\nstatic inline unsigned " << RC.getName()
@ -686,8 +668,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
OS << " };\n";
}
OS << " static const ArrayRef<unsigned> Order[] = {\n"
<< " makeArrayRef(" << RC.getName();
OS << " const MCRegisterClass &MCR = " << Target.getName()
<< "MCRegisterClasses[";
if (!RC.Namespace.empty())
OS << RC.Namespace << "::";
OS << RC.getName() + "RegClassID];"
<< " static const ArrayRef<unsigned> Order[] = {\n"
<< " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
OS << "),\n makeArrayRef(AltOrder" << oi;
OS << ")\n };\n const unsigned Select = " << RC.getName()
@ -821,7 +808,6 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit the constructor of the class...
OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n";
OS << "extern MCRegisterClass " << TargetName << "MCRegisterClasses[];\n";
OS << ClassName << "::" << ClassName
<< "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"