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[MCA] Use references to LSUnitBase in class Scheduler and add helper methods to acquire/release LS queue entries. NFCI 

llvm-svn: 373236
This commit is contained in:
Andrea Di Biagio 2019-09-30 17:24:25 +00:00
parent ad88884658
commit 2730df2e16
3 changed files with 12 additions and 10 deletions
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6
llvm/include/llvm/MCA/HardwareUnits/LSUnit.h
View File

@ -209,8 +209,10 @@ public:
unsigned getUsedLQEntries() const { return UsedLQEntries; }
unsigned getUsedSQEntries() const { return UsedSQEntries; }
unsigned assignLQSlot() { return UsedLQEntries++; }
unsigned assignSQSlot() { return UsedSQEntries++; }
void acquireLQSlot() { ++UsedLQEntries; }
void acquireSQSlot() { ++UsedSQEntries; }
void releaseLQSlot() { --UsedLQEntries; }
void releaseSQSlot() { --UsedSQEntries; }
bool assumeNoAlias() const { return NoAlias; }

8
llvm/include/llvm/MCA/HardwareUnits/Scheduler.h
View File

@ -68,7 +68,7 @@ public:
/// instructions from the dispatch stage, until the write-back stage.
///
class Scheduler : public HardwareUnit {
LSUnit &LSU;
LSUnitBase &LSU;
// Instruction selection strategy for this Scheduler.
std::unique_ptr<SchedulerStrategy> Strategy;
@ -154,15 +154,15 @@ class Scheduler : public HardwareUnit {
bool promoteToPendingSet(SmallVectorImpl<InstRef> &Pending);
public:
Scheduler(const MCSchedModel &Model, LSUnit &Lsu)
Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu)
: Scheduler(Model, Lsu, nullptr) {}
Scheduler(const MCSchedModel &Model, LSUnit &Lsu,
Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu,
std::unique_ptr<SchedulerStrategy> SelectStrategy)
: Scheduler(std::make_unique<ResourceManager>(Model), Lsu,
std::move(SelectStrategy)) {}
Scheduler(std::unique_ptr<ResourceManager> RM, LSUnit &Lsu,
Scheduler(std::unique_ptr<ResourceManager> RM, LSUnitBase &Lsu,
std::unique_ptr<SchedulerStrategy> SelectStrategy)
: LSU(Lsu), Resources(std::move(RM)), BusyResourceUnits(0),
NumDispatchedToThePendingSet(0), HadTokenStall(false) {

8
llvm/lib/MCA/HardwareUnits/LSUnit.cpp
View File

@ -72,9 +72,9 @@ unsigned LSUnit::dispatch(const InstRef &IR) {
assert((Desc.MayLoad || Desc.MayStore) && "Not a memory operation!");
if (Desc.MayLoad)
assignLQSlot();
acquireLQSlot();
if (Desc.MayStore)
assignSQSlot();
acquireSQSlot();
if (Desc.MayStore) {
// Always create a new group for store operations.
@ -173,13 +173,13 @@ void LSUnitBase::onInstructionExecuted(const InstRef &IR) {
}
if (IsALoad) {
UsedLQEntries--;
releaseLQSlot();
LLVM_DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << IR.getSourceIndex()
<< " has been removed from the load queue.\n");
}
if (IsAStore) {
UsedSQEntries--;
releaseSQSlot();
LLVM_DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << IR.getSourceIndex()
<< " has been removed from the store queue.\n");
}