R600: Enable -verify-machineinstrs in some tests.
llvm-svn: 191788
This commit is contained in:
Vincent Lejeune
parent
85f60ef633
commit
269708b98d
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@ -28,7 +28,7 @@
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using namespace llvm;
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AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm)
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: AMDGPUGenInstrInfo(0,0), RI(tm), TM(tm) { }
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: AMDGPUGenInstrInfo(-1,-1), RI(tm), TM(tm) { }
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const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
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return RI;
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@ -118,15 +118,15 @@ class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
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// Multiclass Instruction formats
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//===--------------------------------------------------------------------===//
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// Multiclass that handles branch instructions
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multiclass BranchConditional<SDNode Op> {
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multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> {
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def _i32 : ILFormat<(outs),
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(ins brtarget:$target, GPRI32:$src0),
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(ins brtarget:$target, rci:$src0),
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"; i32 Pseudo branch instruction",
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[(Op bb:$target, GPRI32:$src0)]>;
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[(Op bb:$target, (i32 rci:$src0))]>;
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def _f32 : ILFormat<(outs),
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(ins brtarget:$target, GPRF32:$src0),
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(ins brtarget:$target, rcf:$src0),
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"; f32 Pseudo branch instruction",
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[(Op bb:$target, GPRF32:$src0)]>;
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[(Op bb:$target, (f32 rcf:$src0))]>;
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}
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// Only scalar types should generate flow control
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@ -651,6 +651,11 @@ bool isJump(unsigned Opcode) {
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return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
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}
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static bool isBranch(unsigned Opcode) {
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return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
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Opcode == AMDGPU::BRANCH_COND_f32;
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}
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bool
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R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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@ -669,6 +674,10 @@ R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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return false;
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--I;
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}
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// AMDGPU::BRANCH* instructions are only available after isel and are not
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// handled
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if (isBranch(I->getOpcode()))
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return true;
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if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
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return false;
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}
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@ -2238,7 +2238,7 @@ let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
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def BRANCH : ILFormat<(outs), (ins brtarget:$target),
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"; Pseudo unconditional branch instruction",
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[(br bb:$target)]>;
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defm BRANCH_COND : BranchConditional<IL_brcond>;
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defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>;
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}
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//===---------------------------------------------------------------------===//
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@ -138,8 +138,6 @@ def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X",
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def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,
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(add OQA, OQB, OQAP, OQBP, LDS_DIRECT_A, LDS_DIRECT_B)>;
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} // End isAllocatable = 0
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def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (sequence "KC0_%u_X", 128, 159))>;
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@ -172,6 +170,8 @@ def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32,
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(interleave R600_KC1_X, R600_KC1_Y,
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R600_KC1_Z, R600_KC1_W)>;
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} // End isAllocatable = 0
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def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (sequence "T%u_X", 0, 127), AR_X)>;
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@ -192,6 +192,7 @@ def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
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R600_TReg32,
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R600_ArrayBase,
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R600_Addr,
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R600_KC0, R600_KC1,
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ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF,
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ALU_CONST, ALU_PARAM, OQAP
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)>;
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@ -1,4 +1,4 @@
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;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
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;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
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;REQUIRES: asserts
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define void @main() {
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@ -1,4 +1,4 @@
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;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
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;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
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;REQUIRES: asserts
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define void @main() {
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@ -1,4 +1,4 @@
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;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
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;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
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;REQUIRES: asserts
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define void @main() {
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@ -1,4 +1,4 @@
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;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
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;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
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;REQUIRES: asserts
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define void @main() {
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@ -1,4 +1,4 @@
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;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
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;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
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;REQUIRES: asserts
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define void @main() {
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