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AArch64/ARM64: update Clang after AArch64 removal. 

A few (mostly CodeGen) parts of Clang were tightly coupled to the
AArch64 backend. Now that it's gone, they will not even compile.

I've also deduplicated RUN lines in many of the AArch64 tests. This
might improve "make check-all" time noticably: some of those NEON
tests were monsters.

llvm-svn: 209578
This commit is contained in:
Tim Northover 2014-05-24 12:51:25 +00:00
parent 3b0846e8f7
commit 25e8a6754e
44 changed files with 32 additions and 3652 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
clang/include/clang/Basic/BuiltinsAArch64.def
View File

@ -1,20 +0,0 @@
//===-- BuiltinsAArch64.def - AArch64 Builtin function database -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the AArch64-specific builtin function database. Users of
// this file must define the BUILTIN macro to make use of this information.
//
//===----------------------------------------------------------------------===//
// The format of this database matches clang/Basic/Builtins.def.
// In libgcc
BUILTIN(__clear_cache, "vv*v*", "i")
#undef BUILTIN

10
clang/include/clang/Basic/TargetBuiltins.h
View File

@ -30,16 +30,6 @@ namespace clang {
};
}
/// \brief AArch64 builtins
namespace AArch64 {
enum {
LastTIBuiltin = clang::Builtin::FirstTSBuiltin-1,
LastNEONBuiltin = NEON::FirstTSBuiltin - 1,
#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
#include "clang/Basic/BuiltinsAArch64.def"
LastTSBuiltin
};
}
/// \brief ARM builtins
namespace ARM {
enum {

1
clang/include/clang/Sema/Sema.h
View File

@ -8126,7 +8126,6 @@ private:
bool CheckARMBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
bool CheckARM64BuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
bool CheckAArch64BuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
bool CheckMipsBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
bool CheckX86BuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);

8
clang/lib/AST/ItaniumMangle.cpp
View File

@ -2300,10 +2300,10 @@ void CXXNameMangler::mangleType(const VectorType *T) {
llvm::Triple Target = getASTContext().getTargetInfo().getTriple();
llvm::Triple::ArchType Arch =
getASTContext().getTargetInfo().getTriple().getArch();
if (Arch == llvm::Triple::aarch64 ||
Arch == llvm::Triple::aarch64_be ||
Arch == llvm::Triple::arm64_be ||
(Arch == llvm::Triple::arm64 && !Target.isOSDarwin()))
if ((Arch == llvm::Triple::aarch64 ||
Arch == llvm::Triple::aarch64_be ||
Arch == llvm::Triple::arm64_be ||
Arch == llvm::Triple::arm64) && !Target.isOSDarwin())
mangleAArch64NeonVectorType(T);
else
mangleNeonVectorType(T);

315
clang/lib/Basic/Targets.cpp
View File

@ -3408,289 +3408,6 @@ public:
};
}
namespace {
class AArch64TargetInfo : public TargetInfo {
virtual void setDescriptionString() = 0;
static const char * const GCCRegNames[];
static const TargetInfo::GCCRegAlias GCCRegAliases[];
enum FPUModeEnum {
FPUMode,
NeonMode
};
unsigned FPU;
unsigned CRC;
unsigned Crypto;
static const Builtin::Info BuiltinInfo[];
public:
AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
LongWidth = LongAlign = 64;
LongDoubleWidth = LongDoubleAlign = 128;
PointerWidth = PointerAlign = 64;
SuitableAlign = 128;
WCharType = UnsignedInt;
if (getTriple().getOS() == llvm::Triple::NetBSD) {
WCharType = SignedInt;
Int64Type = SignedLongLong;
IntMaxType = SignedLongLong;
UIntMaxType = UnsignedLongLong;
} else {
WCharType = UnsignedInt;
Int64Type = SignedLong;
IntMaxType = SignedLong;
UIntMaxType = UnsignedLong;
}
LongDoubleFormat = &llvm::APFloat::IEEEquad;
// AArch64 backend supports 64-bit operations at the moment. In principle
// 128-bit is possible if register-pairs are used.
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
TheCXXABI.set(TargetCXXABI::GenericAArch64);
}
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
// GCC defines theses currently
Builder.defineMacro("__aarch64__");
// ACLE predefines. Many can only have one possible value on v8 AArch64.
Builder.defineMacro("__ARM_ACLE", "200");
Builder.defineMacro("__ARM_ARCH", "8");
Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
Builder.defineMacro("__ARM_64BIT_STATE");
Builder.defineMacro("__ARM_PCS_AAPCS64");
Builder.defineMacro("__ARM_ARCH_ISA_A64");
Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
Builder.defineMacro("__ARM_FEATURE_CLZ");
Builder.defineMacro("__ARM_FEATURE_FMA");
Builder.defineMacro("__ARM_FEATURE_DIV");
Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
// 0xe implies support for half, single and double precision operations.
Builder.defineMacro("__ARM_FP", "0xe");
// PCS specifies this for SysV variants, which is all we support. Other ABIs
// may choose __ARM_FP16_FORMAT_ALTERNATIVE.
Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
if (Opts.FastMath || Opts.FiniteMathOnly)
Builder.defineMacro("__ARM_FP_FAST");
if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
Opts.ShortWChar ? "2" : "4");
Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
Opts.ShortEnums ? "1" : "4");
if (FPU == NeonMode) {
Builder.defineMacro("__ARM_NEON");
// 64-bit NEON supports half, single and double precision operations.
Builder.defineMacro("__ARM_NEON_FP", "0xe");
}
if (CRC)
Builder.defineMacro("__ARM_FEATURE_CRC32");
if (Crypto) {
Builder.defineMacro("__ARM_FEATURE_CRYPTO");
}
}
void getTargetBuiltins(const Builtin::Info *&Records,
unsigned &NumRecords) const override {
Records = BuiltinInfo;
NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
}
bool hasFeature(StringRef Feature) const override {
return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode);
}
bool setCPU(const std::string &Name) override {
return llvm::StringSwitch<bool>(Name)
.Case("generic", true)
.Cases("cortex-a53", "cortex-a57", true)
.Default(false);
}
bool handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) override {
FPU = FPUMode;
CRC = 0;
Crypto = 0;
for (unsigned i = 0, e = Features.size(); i != e; ++i) {
if (Features[i] == "+neon")
FPU = NeonMode;
if (Features[i] == "+crc")
CRC = 1;
if (Features[i] == "+crypto")
Crypto = 1;
}
setDescriptionString();
return true;
}
void getGCCRegNames(const char *const *&Names,
unsigned &NumNames) const override;
void getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const override;
bool isCLZForZeroUndef() const override { return false; }
bool validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &Info) const override {
switch (*Name) {
default: return false;
case 'w': // An FP/SIMD vector register
Info.setAllowsRegister();
return true;
case 'I': // Constant that can be used with an ADD instruction
case 'J': // Constant that can be used with a SUB instruction
case 'K': // Constant that can be used with a 32-bit logical instruction
case 'L': // Constant that can be used with a 64-bit logical instruction
case 'M': // Constant that can be used as a 32-bit MOV immediate
case 'N': // Constant that can be used as a 64-bit MOV immediate
case 'Y': // Floating point constant zero
case 'Z': // Integer constant zero
return true;
case 'Q': // A memory reference with base register and no offset
Info.setAllowsMemory();
return true;
case 'S': // A symbolic address
Info.setAllowsRegister();
return true;
case 'U':
// Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
// Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
// Usa: An absolute symbolic address
// Ush: The high part (bits 32:12) of a pc-relative symbolic address
llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
}
}
const char *getClobbers() const override {
// There are no AArch64 clobbers shared by all asm statements.
return "";
}
BuiltinVaListKind getBuiltinVaListKind() const override {
return TargetInfo::AArch64ABIBuiltinVaList;
}
};
const char * const AArch64TargetInfo::GCCRegNames[] = {
"w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
"w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
"w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
"w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
"x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
"b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
"b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
"b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
"b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
"h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
"h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
"h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
"h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
"d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
"d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
"d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
"q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
"q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
"q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
"q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
};
void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
unsigned &NumNames) const {
Names = GCCRegNames;
NumNames = llvm::array_lengthof(GCCRegNames);
}
const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
{ { "x16" }, "ip0"},
{ { "x17" }, "ip1"},
{ { "x29" }, "fp" },
{ { "x30" }, "lr" }
};
void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const {
Aliases = GCCRegAliases;
NumAliases = llvm::array_lengthof(GCCRegAliases);
}
const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
ALL_LANGUAGES },
#include "clang/Basic/BuiltinsNEON.def"
#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
ALL_LANGUAGES },
#include "clang/Basic/BuiltinsAArch64.def"
};
class AArch64leTargetInfo : public AArch64TargetInfo {
void setDescriptionString() override {
DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
}
public:
AArch64leTargetInfo(const llvm::Triple &Triple)
: AArch64TargetInfo(Triple) {
BigEndian = false;
}
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
Builder.defineMacro("__AARCH64EL__");
AArch64TargetInfo::getTargetDefines(Opts, Builder);
}
};
class AArch64beTargetInfo : public AArch64TargetInfo {
void setDescriptionString() override {
DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
}
public:
AArch64beTargetInfo(const llvm::Triple &Triple)
: AArch64TargetInfo(Triple) { }
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
Builder.defineMacro("__AARCH64EB__");
Builder.defineMacro("__AARCH_BIG_ENDIAN");
Builder.defineMacro("__ARM_BIG_ENDIAN");
AArch64TargetInfo::getTargetDefines(Opts, Builder);
}
};
} // end anonymous namespace
namespace {
class ARMTargetInfo : public TargetInfo {
@ -4537,11 +4254,23 @@ class ARM64TargetInfo : public TargetInfo {
public:
ARM64TargetInfo(const llvm::Triple &Triple)
: TargetInfo(Triple), ABI("aapcs") {
if (getTriple().getOS() == llvm::Triple::NetBSD) {
WCharType = SignedInt;
// NetBSD apparently prefers consistency across ARM targets to consistency
// across 64-bit targets.
Int64Type = SignedLongLong;
IntMaxType = SignedLongLong;
UIntMaxType = UnsignedLongLong;
} else {
WCharType = UnsignedInt;
Int64Type = SignedLong;
IntMaxType = SignedLong;
UIntMaxType = UnsignedLong;
}
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
IntMaxType = SignedLong;
UIntMaxType = UnsignedLong;
Int64Type = SignedLong;
WCharType = UnsignedInt;
MaxVectorAlign = 128;
RegParmMax = 8;
MaxAtomicInlineWidth = 128;
@ -6218,21 +5947,21 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
case llvm::Triple::aarch64:
switch (os) {
case llvm::Triple::Linux:
return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
return new LinuxTargetInfo<ARM64leTargetInfo>(Triple);
case llvm::Triple::NetBSD:
return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
return new NetBSDTargetInfo<ARM64leTargetInfo>(Triple);
default:
return new AArch64leTargetInfo(Triple);
return new ARM64leTargetInfo(Triple);
}
case llvm::Triple::aarch64_be:
switch (os) {
case llvm::Triple::Linux:
return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
return new LinuxTargetInfo<ARM64beTargetInfo>(Triple);
case llvm::Triple::NetBSD:
return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
return new NetBSDTargetInfo<ARM64beTargetInfo>(Triple);
default:
return new AArch64beTargetInfo(Triple);
return new ARM64beTargetInfo(Triple);
}
case llvm::Triple::arm:

1307
clang/lib/CodeGen/CGBuiltin.cpp
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File diff suppressed because it is too large Load Diff

2
clang/lib/CodeGen/CodeGenFunction.h
View File

@ -2201,8 +2201,6 @@ public:
const llvm::CmpInst::Predicate Fp,
const llvm::CmpInst::Predicate Ip,
const llvm::Twine &Name = "");
llvm::Value *EmitAArch64CompareBuiltinExpr(llvm::Value *Op, llvm::Type *Ty);
llvm::Value *EmitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E);
llvm::Value *EmitARMBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
llvm::Value *EmitCommonNeonBuiltinExpr(unsigned BuiltinID,

221
clang/lib/CodeGen/TargetInfo.cpp
View File

@ -4511,221 +4511,6 @@ llvm::Value *NaClARMABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
return static_cast<const ABIInfo&>(NInfo).EmitVAArg(VAListAddr, Ty, CGF);
}
//===----------------------------------------------------------------------===//
// AArch64 ABI Implementation
//===----------------------------------------------------------------------===//
namespace {
class AArch64ABIInfo : public ABIInfo {
public:
AArch64ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
private:
// The AArch64 PCS is explicit about return types and argument types being
// handled identically, so we don't need to draw a distinction between
// Argument and Return classification.
ABIArgInfo classifyGenericType(QualType Ty, int &FreeIntRegs,
int &FreeVFPRegs) const;
ABIArgInfo tryUseRegs(QualType Ty, int &FreeRegs, int RegsNeeded, bool IsInt,
llvm::Type *DirectTy = nullptr) const;
void computeInfo(CGFunctionInfo &FI) const override;
llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
CodeGenFunction &CGF) const override;
};
class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
public:
AArch64TargetCodeGenInfo(CodeGenTypes &CGT)
:TargetCodeGenInfo(new AArch64ABIInfo(CGT)) {}
const AArch64ABIInfo &getABIInfo() const {
return static_cast<const AArch64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
}
int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
return 31;
}
bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
llvm::Value *Address) const override {
// 0-31 are x0-x30 and sp: 8 bytes each
llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 31);
// 64-95 are v0-v31: 16 bytes each
llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
AssignToArrayRange(CGF.Builder, Address, Sixteen8, 64, 95);
return false;
}
};
}
void AArch64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
int FreeIntRegs = 8, FreeVFPRegs = 8;
FI.getReturnInfo() = classifyGenericType(FI.getReturnType(),
FreeIntRegs, FreeVFPRegs);
FreeIntRegs = FreeVFPRegs = 8;
for (auto &I : FI.arguments()) {
I.info = classifyGenericType(I.type, FreeIntRegs, FreeVFPRegs);
}
}
ABIArgInfo
AArch64ABIInfo::tryUseRegs(QualType Ty, int &FreeRegs, int RegsNeeded,
bool IsInt, llvm::Type *DirectTy) const {
if (FreeRegs >= RegsNeeded) {
FreeRegs -= RegsNeeded;
return ABIArgInfo::getDirect(DirectTy);
}
llvm::Type *Padding = nullptr;
// We need padding so that later arguments don't get filled in anyway. That
// wouldn't happen if only ByVal arguments followed in the same category, but
// a large structure will simply seem to be a pointer as far as LLVM is
// concerned.
if (FreeRegs > 0) {
if (IsInt)
Padding = llvm::Type::getInt64Ty(getVMContext());
else
Padding = llvm::Type::getFloatTy(getVMContext());
// Either [N x i64] or [N x float].
Padding = llvm::ArrayType::get(Padding, FreeRegs);
FreeRegs = 0;
}
return ABIArgInfo::getIndirect(getContext().getTypeAlign(Ty) / 8,
/*IsByVal=*/ true, /*Realign=*/ false,
Padding);
}
ABIArgInfo AArch64ABIInfo::classifyGenericType(QualType Ty,
int &FreeIntRegs,
int &FreeVFPRegs) const {
// Can only occurs for return, but harmless otherwise.
if (Ty->isVoidType())
return ABIArgInfo::getIgnore();
// Large vector types should be returned via memory. There's no such concept
// in the ABI, but they'd be over 16 bytes anyway so no matter how they're
// classified they'd go into memory (see B.3).
if (Ty->isVectorType() && getContext().getTypeSize(Ty) > 128) {
if (FreeIntRegs > 0)
--FreeIntRegs;
return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
}
// All non-aggregate LLVM types have a concrete ABI representation so they can
// be passed directly. After this block we're guaranteed to be in a
// complicated case.
if (!isAggregateTypeForABI(Ty)) {
// Treat an enum type as its underlying type.
if (const EnumType *EnumTy = Ty->getAs<EnumType>())
Ty = EnumTy->getDecl()->getIntegerType();
if (Ty->isFloatingType() || Ty->isVectorType())
return tryUseRegs(Ty, FreeVFPRegs, /*RegsNeeded=*/ 1, /*IsInt=*/ false);
assert(getContext().getTypeSize(Ty) <= 128 &&
"unexpectedly large scalar type");
int RegsNeeded = getContext().getTypeSize(Ty) > 64 ? 2 : 1;
// If the type may need padding registers to ensure "alignment", we must be
// careful when this is accounted for. Increasing the effective size covers
// all cases.
if (getContext().getTypeAlign(Ty) == 128)
RegsNeeded += FreeIntRegs % 2 != 0;
return tryUseRegs(Ty, FreeIntRegs, RegsNeeded, /*IsInt=*/ true);
}
if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
if (FreeIntRegs > 0 && RAA == CGCXXABI::RAA_Indirect)
--FreeIntRegs;
return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory);
}
if (isEmptyRecord(getContext(), Ty, true)) {
if (!getContext().getLangOpts().CPlusPlus) {
// Empty structs outside C++ mode are a GNU extension, so no ABI can
// possibly tell us what to do. It turns out (I believe) that GCC ignores
// the object for parameter-passsing purposes.
return ABIArgInfo::getIgnore();
}
// The combination of C++98 9p5 (sizeof(struct) != 0) and the pseudocode
// description of va_arg in the PCS require that an empty struct does
// actually occupy space for parameter-passing. I'm hoping for a
// clarification giving an explicit paragraph to point to in future.
return tryUseRegs(Ty, FreeIntRegs, /*RegsNeeded=*/ 1, /*IsInt=*/ true,
llvm::Type::getInt8Ty(getVMContext()));
}
// Homogeneous vector aggregates get passed in registers or on the stack.
const Type *Base = nullptr;
uint64_t NumMembers = 0;
if (isHomogeneousAggregate(Ty, Base, getContext(), &NumMembers)) {
assert(Base && "Base class should be set for homogeneous aggregate");
// Homogeneous aggregates are passed and returned directly.
return tryUseRegs(Ty, FreeVFPRegs, /*RegsNeeded=*/ NumMembers,
/*IsInt=*/ false);
}
uint64_t Size = getContext().getTypeSize(Ty);
if (Size <= 128) {
// Small structs can use the same direct type whether they're in registers
// or on the stack.
llvm::Type *BaseTy;
unsigned NumBases;
int SizeInRegs = (Size + 63) / 64;
if (getContext().getTypeAlign(Ty) == 128) {
BaseTy = llvm::Type::getIntNTy(getVMContext(), 128);
NumBases = 1;
// If the type may need padding registers to ensure "alignment", we must
// be careful when this is accounted for. Increasing the effective size
// covers all cases.
SizeInRegs += FreeIntRegs % 2 != 0;
} else {
BaseTy = llvm::Type::getInt64Ty(getVMContext());
NumBases = SizeInRegs;
}
llvm::Type *DirectTy = llvm::ArrayType::get(BaseTy, NumBases);
return tryUseRegs(Ty, FreeIntRegs, /*RegsNeeded=*/ SizeInRegs,
/*IsInt=*/ true, DirectTy);
}
// If the aggregate is > 16 bytes, it's passed and returned indirectly. In
// LLVM terms the return uses an "sret" pointer, but that's handled elsewhere.
--FreeIntRegs;
return ABIArgInfo::getIndirect(0, /* byVal = */ false);
}
llvm::Value *AArch64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
CodeGenFunction &CGF) const {
int FreeIntRegs = 8, FreeVFPRegs = 8;
Ty = CGF.getContext().getCanonicalType(Ty);
ABIArgInfo AI = classifyGenericType(Ty, FreeIntRegs, FreeVFPRegs);
return EmitAArch64VAArg(VAListAddr, Ty, 8 - FreeIntRegs, 8 - FreeVFPRegs,
AI.isIndirect(), CGF);
}
//===----------------------------------------------------------------------===//
// NVPTX ABI Implementation
//===----------------------------------------------------------------------===//
@ -6684,6 +6469,8 @@ const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
case llvm::Triple::mips64el:
return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, false));
case llvm::Triple::aarch64:
case llvm::Triple::aarch64_be:
case llvm::Triple::arm64:
case llvm::Triple::arm64_be: {
ARM64ABIInfo::ABIKind Kind = ARM64ABIInfo::AAPCS;
@ -6693,10 +6480,6 @@ const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
return *(TheTargetCodeGenInfo = new ARM64TargetCodeGenInfo(Types, Kind));
}
case llvm::Triple::aarch64:
case llvm::Triple::aarch64_be:
return *(TheTargetCodeGenInfo = new AArch64TargetCodeGenInfo(Types));
case llvm::Triple::arm:
case llvm::Triple::armeb:
case llvm::Triple::thumb:

22
clang/lib/Driver/Tools.cpp
View File

@ -444,26 +444,6 @@ void Clang::AddPreprocessingOptions(Compilation &C,
getToolChain().AddClangSystemIncludeArgs(Args, CmdArgs);
}
/// getAArch64TargetCPU - Get the (LLVM) name of the AArch64 cpu we are targeting.
//
// FIXME: tblgen this.
static std::string getAArch64TargetCPU(const ArgList &Args,
const llvm::Triple &Triple) {
// FIXME: Warn on inconsistent use of -mcpu and -march.
// If we have -mcpu=, use that.
if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef MCPU = A->getValue();
// Handle -mcpu=native.
if (MCPU == "native")
return llvm::sys::getHostCPUName();
else
return MCPU;
}
return "generic";
}
// FIXME: Move to target hook.
static bool isSignedCharDefault(const llvm::Triple &Triple) {
switch (Triple.getArch()) {
@ -1345,8 +1325,6 @@ static std::string getCPUName(const ArgList &Args, const llvm::Triple &T) {
case llvm::Triple::aarch64:
case llvm::Triple::aarch64_be:
return getAArch64TargetCPU(Args, T);
case llvm::Triple::arm64:
case llvm::Triple::arm64_be:
return getARM64TargetCPU(Args);

15
clang/lib/Sema/SemaChecking.cpp
View File

@ -309,16 +309,13 @@ Sema::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
if (CheckARMBuiltinFunctionCall(BuiltinID, TheCall))
return ExprError();
break;
case llvm::Triple::aarch64:
case llvm::Triple::aarch64_be:
case llvm::Triple::arm64:
case llvm::Triple::arm64_be:
if (CheckARM64BuiltinFunctionCall(BuiltinID, TheCall))
return ExprError();
break;
case llvm::Triple::aarch64:
case llvm::Triple::aarch64_be:
if (CheckAArch64BuiltinFunctionCall(BuiltinID, TheCall))
return ExprError();
break;
case llvm::Triple::mips:
case llvm::Triple::mipsel:
case llvm::Triple::mips64:
@ -472,14 +469,6 @@ bool Sema::CheckNeonBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
return SemaBuiltinConstantArgRange(TheCall, i, l, u + l);
}
bool Sema::CheckAArch64BuiltinFunctionCall(unsigned BuiltinID,
CallExpr *TheCall) {
if (CheckNeonBuiltinFunctionCall(BuiltinID, TheCall))
return true;
return false;
}
bool Sema::CheckARMBuiltinExclusiveCall(unsigned BuiltinID, CallExpr *TheCall,
unsigned MaxWidth) {
assert((BuiltinID == ARM::BI__builtin_arm_ldrex ||

199
clang/test/CodeGen/aarch64-arguments.c
View File

@ -1,199 +0,0 @@
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -w -o - %s | FileCheck -check-prefix=PCS %s
// Sign extension is performed by the callee on AArch64, which means
// that we *shouldn't* tag arguments and returns with their extension.
// PCS-LABEL: define i8 @f0(i16 %a)
char f0(short a) {
return a;
}
// PCS: define [1 x i64] @f1()
struct s1 { char f0; };
struct s1 f1(void) {}
// PCS: define [1 x i64] @f2()
struct s2 { short f0; };
struct s2 f2(void) {}
// PCS: define [1 x i64] @f3()
struct s3 { int f0; };
struct s3 f3(void) {}
// PCS: define [1 x i64] @f4()
struct s4 { struct s4_0 { int f0; } f0; };
struct s4 f4(void) {}
// PCS: define [1 x i64] @f5()
struct s5 { struct { } f0; int f1; };
struct s5 f5(void) {}
// PCS: define [1 x i64] @f6()
struct s6 { int f0[1]; };
struct s6 f6(void) {}
// PCS-LABEL: define void @f7()
struct s7 { struct { int : 0; } f0; };
struct s7 f7(void) {}
// PCS-LABEL: define void @f8()
struct s8 { struct { int : 0; } f0[1]; };
struct s8 f8(void) {}
// PCS: define [1 x i64] @f9()
struct s9 { long f0; int : 0; };
struct s9 f9(void) {}
// PCS: define [1 x i64] @f10()
struct s10 { long f0; int : 0; int : 0; };
struct s10 f10(void) {}
// PCS: define [1 x i64] @f11()
struct s11 { int : 0; long f0; };
struct s11 f11(void) {}
// PCS: define [1 x i64] @f12()
union u12 { char f0; short f1; int f2; long f3; };
union u12 f12(void) {}
// PCS-LABEL: define %struct.s13 @f13()
struct s13 { float f0; };
struct s13 f13(void) {}
// PCS-LABEL: define %union.u14 @f14()
union u14 { float f0; };
union u14 f14(void) {}
// PCS-LABEL: define void @f15()
void f15(struct s7 a0) {}
// PCS-LABEL: define void @f16()
void f16(struct s8 a0) {}
// PCS: define [1 x i64] @f17()
struct s17 { short f0 : 13; char f1 : 4; };
struct s17 f17(void) {}
// PCS: define [1 x i64] @f18()
struct s18 { short f0; char f1 : 4; };
struct s18 f18(void) {}
// PCS: define [1 x i64] @f19()
struct s19 { long f0; struct s8 f1; };
struct s19 f19(void) {}
// PCS: define [1 x i64] @f20()
struct s20 { struct s8 f1; long f0; };
struct s20 f20(void) {}
// PCS: define [1 x i64] @f21()
struct s21 { struct {} f1; long f0 : 4; };
struct s21 f21(void) {}
// PCS: define { float, float } @f22()
// PCS: define { double, double } @f23(
_Complex float f22(void) {}
_Complex double f23(void) {}
// PCS: define [1 x i64] @f24()
struct s24 { _Complex char f0; };
struct s24 f24() {}
// PCS: define [1 x i64] @f25()
struct s25 { _Complex short f0; };
struct s25 f25() {}
// PCS: define [1 x i64] @f26()
struct s26 { _Complex int f0; };
struct s26 f26() {}
// PCS: define [2 x i64] @f27()
struct s27 { _Complex long f0; };
struct s27 f27() {}
// PCS-LABEL: define void @f28(i8 %a, i16 %b, i32 %c, i64 %d, float %e, double %f)
void f28(char a, short b, int c, long d, float e, double f) {}
// PCS: define void @f29([2 x i64] %a
struct s29 { int arr[4]; };
void f29(struct s29 a) {}
// PCS-LABEL: define void @f30(%struct.s30* %a)
struct s30 { int arr[4]; char c;};
void f30(struct s30 a) {}
// PCS: define void @f31([4 x double] %a
struct s31 { double arr[4]; };
void f31(struct s31 a) {}
// PCS-LABEL: define void @f32(%struct.s32* %a)
struct s32 { float arr[5]; };
void f32(struct s32 a) {}
// Not the only solution, but it *is* an HFA.
// PCS: define void @f33([3 x float] %a.coerce0, float %a.coerce1)
struct s33 { float arr[3]; float a; };
void f33(struct s33 a) {}
// PCS-LABEL: define void @f34(%struct.s34* noalias sret
struct s34 { int a[4]; char b };
struct s34 f34(void) {}
// PCS-LABEL: define void @f35()
struct s35 {};
void f35(struct s35 a) {}
// Check padding is added:
// PCS: @f36(i32 %x0, i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5, i32 %x6, [1 x i64], %struct.s36* byval align 8 %stacked)
struct s36 { long a, b; };
void f36(int x0, int x1, int x2, int x3, int x4, int x5, int x6, struct s36 stacked) {}
// But only once:
// PCS: @f37(i32 %x0, i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5, i32 %x6, [1 x i64], %struct.s37* byval align 8 %stacked, %struct.s37* byval align 8 %stacked2)
struct s37 { long a, b; };
void f37(int x0, int x1, int x2, int x3, int x4, int x5, int x6, struct s37 stacked, struct s37 stacked2) {}
// Check for HFA padding args. Also, they should not end up on the stack in a
// way which will have holes in when lowered further by LLVM. In particular [3 x
// float] would be unacceptable.
// PCS: @f38(float %s0, double %d1, float %s2, float %s3, float %s4, float %s5, [2 x float], %struct.s38* byval align 4 %stacked)
struct s38 { float a, b, c; };
void f38(float s0, double d1, float s2, float s3, float s4, float s5, struct s38 stacked) {}
// Check both VFP and integer arguments are padded (also that pointers and enums
// get counted as integer types correctly).
struct s39_int { long a, b; };
struct s39_float { float a, b, c, d; };
enum s39_enum { Val1, Val2 };
// PCS: @f39(float %s0, i32 %x0, float %s1, i32* %x1, float %s2, i32 %x2, float %s3, float %s4, i32 %x3, [3 x float], %struct.s39_float* byval align 4 %stacked, i32 %x4, i32 %x5, i32 %x6, [1 x i64], %struct.s39_int* byval align 8 %stacked2)
void f39(float s0, int x0, float s1, int *x1, float s2, enum s39_enum x2, float s3, float s4,
int x3, struct s39_float stacked, int x4, int x5, int x6,
struct s39_int stacked2) {}
struct s40 { __int128 a; };
// PCS: @f40(i32 %x0, [1 x i128] %x2_3.coerce, i32 %x4, i32 %x5, i32 %x6, [1 x i64], %struct.s40* byval align 16 %stacked)
void f40(int x0, struct s40 x2_3, int x4, int x5, int x6, struct s40 stacked) {}
// Checking: __int128 will get properly aligned type, with padding so big struct doesn't use x7.
struct s41 { int arr[5]; };
// PCS: @f41(i32 %x0, i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5, i32 %x6, [1 x i64], i128* byval align 16, %struct.s41* %stacked2)
int f41(int x0, int x1, int x2, int x3, int x4, int x5, int x6, __int128 stacked, struct s41 stacked2) {}
// Checking: __int128 needing to be aligned in registers will consume correct
// number. Previously padding was inserted before "stacked" because x6_7 was
// "allocated" to x5 and x6 by clang.
// PCS: @f42(i32 %x0, i32 %x1, i32 %x2, i32 %x3, i32 %x4, i128 %x6_7, i128* byval align 16)
void f42(int x0, int x1, int x2, int x3, int x4, __int128 x6_7, __int128 stacked) {}
// Checking: __fp16 is extended to double when calling variadic functions
void variadic(int a, ...);
void f43(__fp16 *in) {
variadic(42, *in);
// PCS: call void (i32, ...)* @variadic(i32 42, double
}
// Checking: `double' and `long double' have different machine types, so cannot both be in an HFA
struct s44 { long double a; double b; };
// PCS: define void @f44(%struct.s44*
struct s44 f44() {}

1
clang/test/CodeGen/aarch64-inline-asm.c
View File

@ -1,4 +1,3 @@
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s
// The only part clang really deals with is the lvalue/rvalue

5
clang/test/CodeGen/aarch64-neon-2velem.c
View File

@ -1,9 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -O3 -o - %s | FileCheck %s
// Test new aarch64 intrinsics and types

3
clang/test/CodeGen/aarch64-neon-3v.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -O3 -o - %s | FileCheck %s
// Test new aarch64 intrinsics and types

3
clang/test/CodeGen/aarch64-neon-across.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s

1416
clang/test/CodeGen/aarch64-neon-copy.c
View File

File diff suppressed because it is too large Load Diff

3
clang/test/CodeGen/aarch64-neon-extract.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s

3
clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s

5
clang/test/CodeGen/aarch64-neon-fma.c
View File

@ -1,9 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck -check-prefix=CHECK-FMA %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -O3 -o - %s | FileCheck %s
// Test new aarch64 intrinsics and types

13
clang/test/CodeGen/aarch64-neon-intrinsics.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
@ -8294,8 +8291,6 @@ uint64_t test_vsqaddd_u64(uint64_t a, uint64_t b) {
}
int32_t test_vqdmlalh_s16(int32_t a, int16_t b, int16_t c) {
// CHECK-AARCH64-LABEL: test_vqdmlalh_s16
// CHECK-AARCH64: sqdmlal {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
// CHECK-ARM64-LABEL: test_vqdmlalh_s16
// CHECK-ARM64: sqdmull v[[PROD:[0-9]+]].4s, {{v[0-9]+.4h}}, {{v[0-9]+.4h}}
@ -8310,8 +8305,6 @@ int64_t test_vqdmlals_s32(int64_t a, int32_t b, int32_t c) {
}
int32_t test_vqdmlslh_s16(int32_t a, int16_t b, int16_t c) {
// CHECK-AARCH64-LABEL: test_vqdmlslh_s16
// CHECK-AARCH64: sqdmlsl {{s[0-9]+|v[0-9]+.4s}}, {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}
// CHECK-ARM64-LABEL: test_vqdmlslh_s16
// CHECK-ARM64: sqdmull v[[PROD:[0-9]+]].4s, {{v[0-9]+.4h}}, {{v[0-9]+.4h}}
@ -8572,8 +8565,6 @@ int64x1_t test_vshr_n_s64(int64x1_t a) {
}
uint64_t test_vshrd_n_u64(uint64_t a) {
// CHECK-AARCH64-LABEL: test_vshrd_n_u64
// CHECK-AARCH64: {{ushr d[0-9]+, d[0-9]+, #64}}
// CHECK-ARM64-LABEL: test_vshrd_n_u64
// CHECK-ARM64: mov x0, xzr
@ -8581,8 +8572,6 @@ uint64_t test_vshrd_n_u64(uint64_t a) {
}
uint64_t test_vshrd_n_u64_2() {
// CHECK-AARCH64-LABEL: test_vshrd_n_u64_2
// CHECK-AARCH64: {{ushr d[0-9]+, d[0-9]+, #64}}
// CHECK-ARM64-LABEL: test_vshrd_n_u64_2
// CHECK-ARM64: mov x0, xzr
@ -8639,8 +8628,6 @@ uint64_t test_vsrad_n_u64(uint64_t a, uint64_t b) {
}
uint64_t test_vsrad_n_u64_2(uint64_t a, uint64_t b) {
// CHECK-AARCH64-LABEL: test_vsrad_n_u64_2
// CHECK-AARCH64: {{usra d[0-9]+, d[0-9]+, #64}}
// CHECK-ARM64-LABEL: test_vsrad_n_u64_2
// CHECK-ARM64-NOT: add

14
clang/test/CodeGen/aarch64-neon-ld-sideeffect.c
View File

@ -1,14 +0,0 @@
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -emit-llvm -O0 -o - %s | FileCheck %s
#include <arm_neon.h>
void *foo(void);
float32x2_t bar(void) {
// CHECK-LABEL: @bar
return vld1_f32(foo());
// CHECK: call i8* @foo
// CHECK-NOT: call i8* @foo
// CHECK: call <2 x float> @llvm.{{arm|arm64}}.neon.vld1
}

3
clang/test/CodeGen/aarch64-neon-ldst-one.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s

3
clang/test/CodeGen/aarch64-neon-misc.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s

3
clang/test/CodeGen/aarch64-neon-perm.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s

3
clang/test/CodeGen/aarch64-neon-scalar-copy.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s

3
clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s

3
clang/test/CodeGen/aarch64-neon-shifts.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -emit-llvm -O1 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -emit-llvm -O1 -o - %s | FileCheck %s

3
clang/test/CodeGen/aarch64-neon-tbl.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s

3
clang/test/CodeGen/aarch64-neon-vcombine.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -S -O3 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -O3 -o - %s | FileCheck %s
// Test new aarch64 intrinsics and types

17
clang/test/CodeGen/aarch64-neon-vget-hilo.c
View File

@ -1,7 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s --check-prefix CHECK-COMMON --check-prefix CHECK-AARCH64
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s --check-prefix CHECK-COMMON --check-prefix CHECK-ARM64
@ -12,98 +9,84 @@
int8x8_t test_vget_high_s8(int8x16_t a) {
// CHECK-COMMON-LABEL: test_vget_high_s8:
return vget_high_s8(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
int16x4_t test_vget_high_s16(int16x8_t a) {
// CHECK-COMMON-LABEL: test_vget_high_s16:
return vget_high_s16(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
int32x2_t test_vget_high_s32(int32x4_t a) {
// CHECK-COMMON-LABEL: test_vget_high_s32:
return vget_high_s32(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
int64x1_t test_vget_high_s64(int64x2_t a) {
// CHECK-COMMON-LABEL: test_vget_high_s64:
return vget_high_s64(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
uint8x8_t test_vget_high_u8(uint8x16_t a) {
// CHECK-COMMON-LABEL: test_vget_high_u8:
return vget_high_u8(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
uint16x4_t test_vget_high_u16(uint16x8_t a) {
// CHECK-COMMON-LABEL: test_vget_high_u16:
return vget_high_u16(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
uint32x2_t test_vget_high_u32(uint32x4_t a) {
// CHECK-COMMON-LABEL: test_vget_high_u32:
return vget_high_u32(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
uint64x1_t test_vget_high_u64(uint64x2_t a) {
// CHECK-COMMON-LABEL: test_vget_high_u64:
return vget_high_u64(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
poly64x1_t test_vget_high_p64(poly64x2_t a) {
// CHECK-COMMON-LABEL: test_vget_high_p64:
return vget_high_p64(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
float16x4_t test_vget_high_f16(float16x8_t a) {
// CHECK-COMMON-LABEL: test_vget_high_f16:
return vget_high_f16(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
float32x2_t test_vget_high_f32(float32x4_t a) {
// CHECK-COMMON-LABEL: test_vget_high_f32:
return vget_high_f32(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
poly8x8_t test_vget_high_p8(poly8x16_t a) {
// CHECK-COMMON-LABEL: test_vget_high_p8:
return vget_high_p8(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
poly16x4_t test_vget_high_p16(poly16x8_t a) {
// CHECK-COMMON-LABEL: test_vget_high_p16
return vget_high_p16(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}
float64x1_t test_vget_high_f64(float64x2_t a) {
// CHECK-COMMON-LABEL: test_vget_high_f64
return vget_high_f64(a);
// CHECK-AARCH64: dup d0, {{v[0-9]+}}.d[1]
// CHECK-ARM64: ext v0.16b, v0.16b, v0.16b, #8
}

10
clang/test/CodeGen/aarch64-poly128.c
View File

@ -1,8 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s --check-prefix=CHECK \
// RUN: --check-prefix=CHECK-AARCH64
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s --check-prefix=CHECK \
// RUN: --check-prefix=CHECK-ARM64
@ -19,8 +15,6 @@
void test_vstrq_p128(poly128_t * ptr, poly128_t val) {
// CHECK-LABEL: test_vstrq_p128
vstrq_p128(ptr, val);
// CHECK-AARCH64: str {{x[0-9]+}}, [{{x[0-9]+}}, #8]
// CHECK-AARCH64-NEXT: str {{x[0-9]+}}, [{{x[0-9]+}}]
// CHECK-ARM64: stp {{x[0-9]+}}, {{x[0-9]+}}, [x0]
}
@ -28,8 +22,6 @@ void test_vstrq_p128(poly128_t * ptr, poly128_t val) {
poly128_t test_vldrq_p128(poly128_t * ptr) {
// CHECK-LABEL: test_vldrq_p128
return vldrq_p128(ptr);
// CHECK-AARCH64: ldr {{x[0-9]+}}, [{{x[0-9]+}}]
// CHECK-AARCH64-NEXT: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8]
// CHECK-ARM64: ldp {{x[0-9]+}}, {{x[0-9]+}}, [x0]
}
@ -37,8 +29,6 @@ poly128_t test_vldrq_p128(poly128_t * ptr) {
void test_ld_st_p128(poly128_t * ptr) {
// CHECK-LABEL: test_ld_st_p128
vstrq_p128(ptr+1, vldrq_p128(ptr));
// CHECK-AARCH64: ldr {{q[0-9]+}}, [{{x[0-9]+}}]
// CHECK-AARCH64-NEXT: str {{q[0-9]+}}, [{{x[0-9]+}}, #16]
// CHECK-ARM64: ldp [[PLO:x[0-9]+]], [[PHI:x[0-9]+]], [{{x[0-9]+}}]
// CHECK-ARM64-NEXT: stp [[PLO]], [[PHI]], [{{x[0-9]+}}, #16]

16
clang/test/CodeGen/aarch64-poly64.c
View File

@ -1,8 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s --check-prefix=CHECK \
// RUN: --check-prefix=CHECK-AARCH64
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s --check-prefix=CHECK \
// RUN: --check-prefix=CHECK-ARM64
@ -74,7 +70,6 @@ poly64x2_t test_vsetq_lane_p64(poly64_t a, poly64x2_t v) {
poly64x1_t test_vcopy_lane_p64(poly64x1_t a, poly64x1_t b) {
// CHECK-LABEL: test_vcopy_lane_p64
return vcopy_lane_p64(a, 0, b, 0);
// CHECK-AARCH64: fmov {{d[0-9]+}}, {{d[0-9]+}}
// CHECK-ARM64: mov v0.16b, v1.16b
}
@ -88,7 +83,6 @@ poly64x2_t test_vcopyq_lane_p64(poly64x2_t a, poly64x1_t b) {
poly64x2_t test_vcopyq_laneq_p64(poly64x2_t a, poly64x2_t b) {
// CHECK-LABEL: test_vcopyq_laneq_p64
return vcopyq_laneq_p64(a, 1, b, 1);
// CHECK-AARCH64: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[1]
}
poly64x1_t test_vcreate_p64(uint64_t a) {
@ -135,28 +129,24 @@ poly64x2_t test_vcombine_p64(poly64x1_t low, poly64x1_t high) {
poly64x1_t test_vld1_p64(poly64_t const * ptr) {
// CHECK-LABEL: test_vld1_p64
return vld1_p64(ptr);
// CHECK-AARCH64: ld1 { {{v[0-9]+}}.1d }, [{{x[0-9]+|sp}}]
// CHECK-ARM64: ldr {{d[0-9]+}}, [{{x[0-9]+|sp}}]
}
poly64x2_t test_vld1q_p64(poly64_t const * ptr) {
// CHECK-LABEL: test_vld1q_p64
return vld1q_p64(ptr);
// CHECK-AARCH64: ld1 { {{v[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
// CHECK-ARM64: ldr {{q[0-9]+}}, [{{x[0-9]+|sp}}]
}
void test_vst1_p64(poly64_t * ptr, poly64x1_t val) {
// CHECK-LABEL: test_vst1_p64
return vst1_p64(ptr, val);
// CHECK-AARCH64: st1 { {{v[0-9]+}}.1d }, [{{x[0-9]+|sp}}]
// CHECK-ARM64: str {{d[0-9]+}}, [{{x[0-9]+|sp}}]
}
void test_vst1q_p64(poly64_t * ptr, poly64x2_t val) {
// CHECK-LABEL: test_vst1q_p64
return vst1q_p64(ptr, val);
// CHECK-AARCH64: st1 { {{v[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
// CHECK-ARM64: str {{q[0-9]+}}, [{{x[0-9]+|sp}}]
}
@ -247,42 +237,36 @@ poly64x2_t test_vextq_p64(poly64x2_t a, poly64x2_t b) {
poly64x2_t test_vzip1q_p64(poly64x2_t a, poly64x2_t b) {
// CHECK-LABEL: test_vzip1q_p64
return vzip1q_p64(a, b);
// CHECK-AARCH64: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
// CHECK-ARM64: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
}
poly64x2_t test_vzip2q_p64(poly64x2_t a, poly64x2_t b) {
// CHECK-LABEL: test_vzip2q_p64
return vzip2q_u64(a, b);
// CHECK-AARCH64: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1]
// CHECK-ARM64: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
}
poly64x2_t test_vuzp1q_p64(poly64x2_t a, poly64x2_t b) {
// CHECK-LABEL: test_vuzp1q_p64
return vuzp1q_p64(a, b);
// CHECK-AARCH64: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
// CHECK-ARM64: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
}
poly64x2_t test_vuzp2q_p64(poly64x2_t a, poly64x2_t b) {
// CHECK-LABEL: test_vuzp2q_p64
return vuzp2q_u64(a, b);
// CHECK-AARCH64: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1]
// CHECK-ARM64: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
}
poly64x2_t test_vtrn1q_p64(poly64x2_t a, poly64x2_t b) {
// CHECK-LABEL: test_vtrn1q_p64
return vtrn1q_p64(a, b);
// CHECK-AARCH64: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
// CHECK-ARM64: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
}
poly64x2_t test_vtrn2q_p64(poly64x2_t a, poly64x2_t b) {
// CHECK-LABEL: test_vtrn2q_p64
return vtrn2q_u64(a, b);
// CHECK-AARCH64: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1]
// CHECK-ARM64: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
}

3
clang/test/CodeGen/aarch64-type-sizes.c
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@ -1,6 +1,3 @@
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -w -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
// RUN: %clang_cc1 -triple aarch64_be-none-linux-gnu -emit-llvm -w -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
// RUN: %clang_cc1 -triple arm64_be-none-linux-gnu -emit-llvm -w -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
// char by definition has size 1

2
clang/test/CodeGen/aarch64-varargs.c
View File

@ -1,5 +1,3 @@
// RUN: %clang_cc1 -triple aarch64 -emit-llvm -o - %s | FileCheck -check-prefix=CHECK --check-prefix=CHECK-LE %s
// RUN: %clang_cc1 -triple aarch64_be -emit-llvm -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
// RUN: %clang_cc1 -triple arm64-linux-gnu -emit-llvm -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
// RUN: %clang_cc1 -triple arm64_be-linux-gnu -emit-llvm -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s

6
clang/test/CodeGen/builtins-aarch64.c
View File

@ -1,6 +0,0 @@
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -O3 -emit-llvm -o - %s | FileCheck %s
void f0(char *a, char *b) {
__clear_cache(a,b);
// CHECK: call {{.*}} @__clear_cache
}

1
clang/test/CodeGen/named_reg_global.c
View File

@ -1,5 +1,4 @@
// RUN: %clang_cc1 -triple x86_64-linux-gnu -S -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-linux-gnu -S -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -triple arm64-linux-gnu -S -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -triple armv7-linux-gnu -S -emit-llvm %s -o - | FileCheck %s

4
clang/test/CodeGen/neon-crypto.c
View File

@ -1,9 +1,5 @@
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -target-feature +crypto -emit-llvm -O1 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm-none-linux-gnueabi -target-feature +neon \
// RUN: -target-feature +crypto -target-cpu cortex-a57 -emit-llvm -O1 -o - %s | FileCheck %s
// RUN: not %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -S -O3 -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -target-feature +crypto -emit-llvm -O1 -o - %s | FileCheck %s

2
clang/test/CodeGen/target-data.c
View File

@ -122,8 +122,6 @@
// RUN: | FileCheck %s -check-prefix=R600SI
// R600SI: target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
// RUN: %clang_cc1 -triple aarch64-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=AARCH64
// RUN: %clang_cc1 -triple arm64-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=AARCH64
// AARCH64: target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"

1
clang/test/CodeGenCXX/aarch64-arguments.cpp
View File

@ -1,4 +1,3 @@
// RUN: %clang_cc1 -triple aarch64-none-linux -emit-llvm -w -o - %s | FileCheck -check-prefix=PCS %s
// RUN: %clang_cc1 -triple arm64-none-linux -emit-llvm -w -o - %s | FileCheck -check-prefix=PCS %s
// PCS: define void @{{.*}}(i8 %a

1
clang/test/CodeGenCXX/aarch64-cxxabi.cpp
View File

@ -1,4 +1,3 @@
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -w -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -emit-llvm -w -o - %s | FileCheck %s
// Check differences between the generic Itanium ABI, the AArch32 version and

2
clang/test/CodeGenCXX/aarch64-mangle-neon-vectors.cpp
View File

@ -1,6 +1,4 @@
// REQUIRES: aarch64-registered-target
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon %s -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon %s -emit-llvm -o - | FileCheck %s
typedef unsigned char uint8_t;

3
clang/test/CodeGenCXX/aarch64-neon.cpp
View File

@ -1,6 +1,3 @@
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s

5
clang/test/CodeGenCXX/int64_uint64.cpp
View File

@ -3,11 +3,6 @@
// RUN: -target-cpu cortex-a8 \
// RUN: -emit-llvm -w -O1 -o - %s | FileCheck --check-prefix=CHECK-ARM %s
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64-linux-gnueabi \
// RUN: -target-feature +neon \
// RUN: -emit-llvm -w -O1 -o - %s | FileCheck --check-prefix=CHECK-AARCH64 %s
// REQUIRES: arm64-registered-target
// RUN: %clang_cc1 -triple arm64-linux-gnueabi \
// RUN: -target-feature +neon \

1
clang/test/Sema/atomic-ops.c
View File

@ -1,5 +1,4 @@
// RUN: %clang_cc1 %s -verify -fsyntax-only -triple=i686-linux-gnu -std=c11
// RUN: %clang_cc1 %s -verify -fsyntax-only -triple=aarch64-linux-gnu -std=c11
// Basic parsing/Sema tests for __c11_atomic_*