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[mips] Extend range of register indexes accepted by cfcmsa/ctcmsa 

The `cfcmsa` and `ctcmsa` instructions accept index of MSA control
register. The MIPS64 SIMD Architecture define eight MSA control
registers. But register index for `cfcmsa` and `ctcmsa` instructions
might be any number in 0..31 range. If the index is greater then 7,
`cfcmsa` writes zero to the destination registers and `ctcmsa` does
nothing [1].

[1] MIPS Architecture for Programmers Volume IV-j:
    The MIPS64 SIMD Architecture Module
https://www.mips.com/?do-download=the-mips64-simd-architecture-module

Differential Revision: https://reviews.llvm.org/D62597

llvm-svn: 362299
This commit is contained in:
Simon Atanasyan 2019-06-01 13:55:18 +00:00
parent 45eb4c7e55
commit 25694e0084
3 changed files with 27 additions and 13 deletions
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8
llvm/lib/Target/Mips/MipsRegisterInfo.td
View File

@ -258,6 +258,11 @@ let Namespace = "Mips" in {
def MSARequest : MipsReg<5, "5">;
def MSAMap : MipsReg<6, "6">;
def MSAUnmap : MipsReg<7, "7">;
// MSA-ASE fake control registers.
// These registers do not exist, but instructions like `cfcmsa`
// and `ctcmsa` allows to specify them.
foreach I = 8-31 in
def MSA#I : MipsReg<#I, ""#I>;
// Octeon multiplier and product registers
def MPL0 : MipsReg<0, "mpl0">;
@ -438,7 +443,8 @@ def MSA128WEvens: RegisterClass<"Mips", [v4i32, v4f32], 128,
(decimate (sequence "W%u", 0, 31), 2)>;
def MSACtrl: RegisterClass<"Mips", [i32], 32, (add
MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>;
MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap,
(sequence "MSA%u", 8, 31))>, Unallocatable;
// Hi/Lo Registers
def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;

14
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@ -75,18 +75,8 @@ void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
}
unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
default:
llvm_unreachable("Could not map int to register");
case 0: return Mips::MSAIR;
case 1: return Mips::MSACSR;
case 2: return Mips::MSAAccess;
case 3: return Mips::MSASave;
case 4: return Mips::MSAModify;
case 5: return Mips::MSARequest;
case 6: return Mips::MSAMap;
case 7: return Mips::MSAUnmap;
}
uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue();
return Mips::MSACtrlRegClass.getRegister(RegNum);
}
bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,

18
llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
View File

@ -84,6 +84,15 @@ entry:
; CHECK: cfcmsa $[[R1:[0-9]+]], $7
; CHECK: .size msa_unmap_cfcmsa_test
;
define i32 @msa_invalid_reg_cfcmsa_test() nounwind {
entry:
%0 = tail call i32 @llvm.mips.cfcmsa(i32 8)
ret i32 %0
}
; CHECK-LABEL: msa_invalid_reg_cfcmsa_test:
; CHECK: cfcmsa ${{[0-9]+}}, $8
;
define void @msa_ir_ctcmsa_test() nounwind {
entry:
tail call void @llvm.mips.ctcmsa(i32 0, i32 1)
@ -164,5 +173,14 @@ entry:
; CHECK: ctcmsa $7
; CHECK: .size msa_unmap_ctcmsa_test
;
define void @msa_invalid_reg_ctcmsa_test() nounwind {
entry:
tail call void @llvm.mips.ctcmsa(i32 8, i32 1)
ret void
}
; CHECK: msa_invalid_reg_ctcmsa_test:
; CHECK: ctcmsa $8
;
declare i32 @llvm.mips.cfcmsa(i32) nounwind
declare void @llvm.mips.ctcmsa(i32, i32) nounwind