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R600/SI: Add exec_lo and exec_hi subregisters. 

This allows accessing an SReg subregister with a normal subregister
index, instead of getting a machine verifier error.

Also be sure to include all of these subregisters in SReg_32.
This fixes inferring SGPR instead of SReg when finding a
super register class.

llvm-svn: 214901
This commit is contained in:
Matt Arsenault 2014-08-05 17:52:37 +00:00
parent 2efa42c937
commit 2549bb4b83
1 changed files with 10 additions and 2 deletions
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12
llvm/lib/Target/R600/SIRegisterInfo.td
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@ -27,7 +27,15 @@ def VCC : RegisterWithSubRegs<"VCC", [VCC_LO, VCC_HI]> {
let HWEncoding = 106; let HWEncoding = 106;
} }
def EXEC : SIReg<"EXEC", 126>; def EXEC_LO : SIReg<"EXEC", 126>;
def EXEC_HI : SIReg<"EXEC", 127>;
def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]> {
let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1];
let HWEncoding = 126;
}
def SCC : SIReg<"SCC", 253>; def SCC : SIReg<"SCC", 253>;
def M0 : SIReg <"M0", 124>; def M0 : SIReg <"M0", 124>;
@ -159,7 +167,7 @@ def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
// Register class for all scalar registers (SGPRs + Special Registers) // Register class for all scalar registers (SGPRs + Special Registers)
def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
(add SGPR_32, M0Reg, VCC_LO) (add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI)
>; >;
def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64], 64, (add SGPR_64Regs)>; def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64], 64, (add SGPR_64Regs)>;