From 2549bb4b83cbf9fe3d757e47f1ec26330e994e7e Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 5 Aug 2014 17:52:37 +0000 Subject: [PATCH] R600/SI: Add exec_lo and exec_hi subregisters. This allows accessing an SReg subregister with a normal subregister index, instead of getting a machine verifier error. Also be sure to include all of these subregisters in SReg_32. This fixes inferring SGPR instead of SReg when finding a super register class. llvm-svn: 214901 --- llvm/lib/Target/R600/SIRegisterInfo.td | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/R600/SIRegisterInfo.td b/llvm/lib/Target/R600/SIRegisterInfo.td index 8974b6300625..3921ec7c3ae4 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.td +++ b/llvm/lib/Target/R600/SIRegisterInfo.td @@ -27,7 +27,15 @@ def VCC : RegisterWithSubRegs<"VCC", [VCC_LO, VCC_HI]> { let HWEncoding = 106; } -def EXEC : SIReg<"EXEC", 126>; +def EXEC_LO : SIReg<"EXEC", 126>; +def EXEC_HI : SIReg<"EXEC", 127>; + +def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]> { + let Namespace = "AMDGPU"; + let SubRegIndices = [sub0, sub1]; + let HWEncoding = 126; +} + def SCC : SIReg<"SCC", 253>; def M0 : SIReg <"M0", 124>; @@ -159,7 +167,7 @@ def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>; // Register class for all scalar registers (SGPRs + Special Registers) def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, - (add SGPR_32, M0Reg, VCC_LO) + (add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI) >; def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64], 64, (add SGPR_64Regs)>;