[Hexagon] Simplify A4_rcmp[n]eqi R, 0
Consider cases when register R is known to be zero/non-zero, or when it is defined by a C2_muxii instruction. llvm-svn: 338251
This commit is contained in:
Krzysztof Parzyszek
parent
898cd398d3
commit
24fae50905
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@ -1777,6 +1777,7 @@ namespace {
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const BitTracker::RegisterCell &RC);
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bool simplifyExtractLow(MachineInstr *MI, BitTracker::RegisterRef RD,
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const BitTracker::RegisterCell &RC, const RegisterSet &AVs);
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bool simplifyRCmp0(MachineInstr *MI, BitTracker::RegisterRef RD);
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// Cache of created instructions to avoid creating duplicates.
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// XXX Currently only used by genBitSplit.
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@ -2567,6 +2568,127 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI,
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return Changed;
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}
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bool BitSimplification::simplifyRCmp0(MachineInstr *MI,
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BitTracker::RegisterRef RD) {
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unsigned Opc = MI->getOpcode();
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if (Opc != Hexagon::A4_rcmpeqi && Opc != Hexagon::A4_rcmpneqi)
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return false;
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MachineOperand &CmpOp = MI->getOperand(2);
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if (!CmpOp.isImm() || CmpOp.getImm() != 0)
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return false;
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const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI);
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if (FRC != &Hexagon::IntRegsRegClass && FRC != &Hexagon::DoubleRegsRegClass)
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return false;
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assert(RD.Sub == 0);
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MachineBasicBlock &B = *MI->getParent();
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const DebugLoc &DL = MI->getDebugLoc();
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auto At = MI->isPHI() ? B.getFirstNonPHI()
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: MachineBasicBlock::iterator(MI);
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bool KnownZ = true;
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bool KnownNZ = false;
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BitTracker::RegisterRef SR = MI->getOperand(1);
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if (!BT.has(SR.Reg))
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return false;
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const BitTracker::RegisterCell &SC = BT.lookup(SR.Reg);
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unsigned F, W;
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if (!HBS::getSubregMask(SR, F, W, MRI))
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return false;
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for (uint16_t I = F; I != F+W; ++I) {
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const BitTracker::BitValue &V = SC[I];
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if (!V.is(0))
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KnownZ = false;
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if (V.is(1))
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KnownNZ = true;
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}
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auto ReplaceWithConst = [&] (int C) {
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unsigned NewR = MRI.createVirtualRegister(FRC);
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BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrsi), NewR)
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.addImm(C);
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HBS::replaceReg(RD.Reg, NewR, MRI);
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BitTracker::RegisterCell NewRC(W);
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for (uint16_t I = 0; I != W; ++I) {
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NewRC[I] = BitTracker::BitValue(C & 1);
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C = unsigned(C) >> 1;
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}
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BT.put(BitTracker::RegisterRef(NewR), NewRC);
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return true;
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};
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auto IsNonZero = [] (const MachineOperand &Op) {
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if (Op.isGlobal() || Op.isBlockAddress())
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return true;
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if (Op.isImm())
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return Op.getImm() != 0;
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if (Op.isCImm())
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return !Op.getCImm()->isZero();
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if (Op.isFPImm())
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return !Op.getFPImm()->isZero();
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return false;
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};
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auto IsZero = [] (const MachineOperand &Op) {
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if (Op.isGlobal() || Op.isBlockAddress())
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return false;
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if (Op.isImm())
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return Op.getImm() == 0;
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if (Op.isCImm())
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return Op.getCImm()->isZero();
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if (Op.isFPImm())
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return Op.getFPImm()->isZero();
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return false;
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};
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// If the source register is known to be 0 or non-0, the comparison can
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// be folded to a load of a constant.
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if (KnownZ || KnownNZ) {
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assert(KnownZ != KnownNZ && "Register cannot be both 0 and non-0");
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return ReplaceWithConst(KnownZ == (Opc == Hexagon::A4_rcmpeqi));
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}
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// Special case: if the compare comes from a C2_muxii, then we know the
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// two possible constants that can be the source value.
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MachineInstr *InpDef = MRI.getVRegDef(SR.Reg);
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if (!InpDef)
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return false;
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if (SR.Sub == 0 && InpDef->getOpcode() == Hexagon::C2_muxii) {
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MachineOperand &Src1 = InpDef->getOperand(2);
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MachineOperand &Src2 = InpDef->getOperand(3);
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// Check if both are non-zero.
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bool KnownNZ1 = IsNonZero(Src1), KnownNZ2 = IsNonZero(Src2);
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if (KnownNZ1 && KnownNZ2)
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return ReplaceWithConst(Opc == Hexagon::A4_rcmpneqi);
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// Check if both are zero.
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bool KnownZ1 = IsZero(Src1), KnownZ2 = IsZero(Src2);
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if (KnownZ1 && KnownZ2)
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return ReplaceWithConst(Opc == Hexagon::A4_rcmpeqi);
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// If for both operands we know that they are either 0 or non-0,
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// replace the comparison with a C2_muxii, using the same predicate
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// register, but with operands substituted with 0/1 accordingly.
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if ((KnownZ1 || KnownNZ1) && (KnownZ2 || KnownNZ2)) {
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unsigned NewR = MRI.createVirtualRegister(FRC);
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BuildMI(B, At, DL, HII.get(Hexagon::C2_muxii), NewR)
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.addReg(InpDef->getOperand(1).getReg())
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.addImm(KnownZ1 == (Opc == Hexagon::A4_rcmpeqi))
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.addImm(KnownZ2 == (Opc == Hexagon::A4_rcmpeqi));
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HBS::replaceReg(RD.Reg, NewR, MRI);
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// Create a new cell with only the least significant bit unknown.
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BitTracker::RegisterCell NewRC(W);
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NewRC[0] = BitTracker::BitValue::self();
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NewRC.fill(1, W, BitTracker::BitValue::Zero);
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BT.put(BitTracker::RegisterRef(NewR), NewRC);
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return true;
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}
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}
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return false;
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}
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bool BitSimplification::processBlock(MachineBasicBlock &B,
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const RegisterSet &AVs) {
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if (!BT.reached(&B))
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@ -2615,6 +2737,7 @@ bool BitSimplification::processBlock(MachineBasicBlock &B,
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T = T || genExtractHalf(MI, RD, RC);
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T = T || genCombineHalf(MI, RD, RC);
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T = T || genExtractLow(MI, RD, RC);
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T = T || simplifyRCmp0(MI, RD);
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Changed |= T;
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continue;
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}
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@ -347,9 +347,11 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI,
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return rr0(RC, Outputs);
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}
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case C2_tfrrp: {
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RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
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W0 = 8; // XXX Pred size
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return rr0(eINS(RC, eXTR(rc(1), 0, W0), 0), Outputs);
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uint16_t RW = W0;
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uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
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RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW);
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RC.fill(PW, RW, BT::BitValue::Zero);
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return rr0(eINS(RC, eXTR(rc(1), 0, PW), 0), Outputs);
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}
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// Arithmetic:
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@ -950,6 +952,19 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI,
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}
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default:
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// For instructions that define a single predicate registers, store
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// the low 8 bits of the register only.
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if (unsigned DefR = getUniqueDefVReg(MI)) {
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if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) {
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BT::RegisterRef PD(DefR, 0);
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uint16_t RW = getRegBitWidth(PD);
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uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
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RegisterCell RC = RegisterCell::self(DefR, RW);
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RC.fill(PW, RW, BT::BitValue::Zero);
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putCell(PD, RC, Outputs);
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return true;
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}
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}
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return MachineEvaluator::evaluate(MI, Inputs, Outputs);
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}
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#undef im
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@ -1016,6 +1031,21 @@ bool HexagonEvaluator::evaluate(const MachineInstr &BI,
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return true;
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}
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unsigned HexagonEvaluator::getUniqueDefVReg(const MachineInstr &MI) const {
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unsigned DefReg = 0;
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for (const MachineOperand &Op : MI.operands()) {
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if (!Op.isReg() || !Op.isDef())
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continue;
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unsigned R = Op.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(R))
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continue;
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if (DefReg != 0)
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return 0;
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DefReg = R;
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}
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return DefReg;
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}
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bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
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const CellMapType &Inputs,
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CellMapType &Outputs) const {
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@ -49,6 +49,7 @@ struct HexagonEvaluator : public BitTracker::MachineEvaluator {
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const HexagonInstrInfo &TII;
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private:
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unsigned getUniqueDefVReg(const MachineInstr &MI) const;
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bool evaluateLoad(const MachineInstr &MI, const CellMapType &Inputs,
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CellMapType &Outputs) const;
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bool evaluateFormalCopy(const MachineInstr &MI, const CellMapType &Inputs,
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@ -0,0 +1,154 @@
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# RUN: llc -march=hexagon -run-pass hexagon-bit-simplify -o - %s | FileCheck %s
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--- |
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@g0 = global i32 0, align 4
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define i32 @f0() { ret i32 0 }
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define i32 @f1() { ret i32 0 }
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define i32 @f2() { ret i32 0 }
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define i32 @f3() { ret i32 0 }
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define i32 @f4() { ret i32 0 }
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define i32 @f5() { ret i32 0 }
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define i32 @f6() { ret i32 0 }
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define i32 @f7() { ret i32 0 }
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...
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# Case 0: is-zero with known zero register
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# CHECK-LABEL: name: f0
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# CHECK: %[[R00:[0-9]+]]:intregs = A2_tfrsi 1
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# CHECK: $r0 = COPY %[[R00]]
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# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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name: f0
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:intregs = A2_tfrsi 0
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%2:intregs = A4_rcmpeqi killed %0, 0
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$r0 = COPY %2
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PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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...
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# Case 1: is-zero with known non-zero register
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# CHECK-LABEL: name: f1
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# CHECK: %[[R10:[0-9]+]]:intregs = A2_tfrsi 0
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# CHECK: $r0 = COPY %[[R10]]
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# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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name: f1
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:intregs = A2_tfrsi 128
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%2:intregs = A4_rcmpeqi killed %0, 0
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$r0 = COPY %2
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PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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...
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# Case 2: is-not-zero with known zero register
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# CHECK-LABEL: name: f2
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# CHECK: %[[R20:[0-9]+]]:intregs = A2_tfrsi 0
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# CHECK: $r0 = COPY %[[R20]]
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# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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name: f2
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:intregs = A2_tfrsi 0
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%2:intregs = A4_rcmpneqi killed %0, 0
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$r0 = COPY %2
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PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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...
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# Case 3: is-not-zero with known non-zero register
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# CHECK-LABEL: name: f3
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# CHECK: %[[R30:[0-9]+]]:intregs = A2_tfrsi 1
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# CHECK: $r0 = COPY %[[R30]]
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# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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name: f3
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:intregs = A2_tfrsi 1024
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%2:intregs = A4_rcmpneqi killed %0, 0
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$r0 = COPY %2
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PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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...
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# Case 4: is-zero with mux(p, 1, 0)
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# CHECK-LABEL: name: f4
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# CHECK: %[[R40:[0-9]+]]:predregs = COPY $p0
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# CHECK: %[[R41:[0-9]+]]:intregs = C2_muxii %[[R40]], 0, 1
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# CHECK: $r0 = COPY %[[R41]]
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# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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name: f4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0
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%0:predregs = COPY $p0
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%1:intregs = C2_muxii %0, 1, 0
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%2:intregs = A4_rcmpeqi killed %1, 0
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$r0 = COPY %2
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PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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...
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# Case 5: is-zero with mux(p, 0, 1)
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# CHECK-LABEL: name: f5
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# CHECK: %[[R50:[0-9]+]]:predregs = COPY $p0
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# CHECK: %[[R51:[0-9]+]]:intregs = C2_muxii %[[R50]], 1, 0
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# CHECK: $r0 = COPY %[[R51]]
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# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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name: f5
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0
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%0:predregs = COPY $p0
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%1:intregs = C2_muxii %0, 0, 1
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%2:intregs = A4_rcmpeqi killed %1, 0
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$r0 = COPY %2
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PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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...
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# Case 6: is-not-zero with mux(p, 1, 2)
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# CHECK-LABEL: name: f6
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# CHECK: %[[R60:[0-9]+]]:intregs = A2_tfrsi 1
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# CHECK: $r0 = COPY %[[R60]]
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# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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name: f6
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0
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%0:predregs = COPY $p0
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%1:intregs = C2_muxii %0, 1, 2
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%2:intregs = A4_rcmpneqi killed %1, 0
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$r0 = COPY %2
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PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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...
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# Case 7: is-not-zero with mux(p, @g0, 2)
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# CHECK-LABEL: name: f7
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# CHECK: %[[R70:[0-9]+]]:intregs = A2_tfrsi 1
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# CHECK: $r0 = COPY %[[R70]]
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# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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name: f7
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0
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%0:predregs = COPY $p0
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%1:intregs = C2_muxii %0, @g0, 2
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%2:intregs = A4_rcmpneqi killed %1, 0
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$r0 = COPY %2
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PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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...
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