It's error-prone to maintain two separate variants of asmprinting stuff, one of which is even used. Drop second (aka 'intel') variant of operands. It can be added later, if needed.
llvm-svn: 70745
This commit is contained in:
Anton Korobeynikov
parent
b6321e15f7
commit
24bfb51416
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@ -169,51 +169,51 @@ def PUSH16r : Pseudo<(outs), (ins GR16:$reg), "push.w\t$reg",[]>;
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// FIXME: Provide proper encoding!
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let neverHasSideEffects = 1 in {
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def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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"mov.b\t{$src, $dst}",
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[]>;
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def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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"mov.w\t{$src, $dst}",
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[]>;
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}
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// FIXME: Provide proper encoding!
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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"mov.b\t{$src, $dst}",
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[(set GR8:$dst, imm:$src)]>;
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def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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"mov.w\t{$src, $dst}",
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[(set GR16:$dst, imm:$src)]>;
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}
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let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
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def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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"mov.b\t{$src, $dst}",
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[(set GR8:$dst, (load addr:$src))]>;
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def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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"mov.w\t{$src, $dst}",
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[(set GR16:$dst, (load addr:$src))]>;
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}
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def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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"mov.b\t{$src, $dst}",
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[(set GR16:$dst, (zext GR8:$src))]>;
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def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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"mov.b\t{$src, $dst}",
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[(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
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def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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"mov.b\t{$src, $dst}",
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[(store (i8 imm:$src), addr:$dst)]>;
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def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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"mov.w\t{$src, $dst}",
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[(store (i16 imm:$src), addr:$dst)]>;
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def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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"mov.b\t{$src, $dst}",
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[(store GR8:$src, addr:$dst)]>;
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def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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"mov.w\t{$src, $dst}",
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[(store GR16:$src, addr:$dst)]>;
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//===----------------------------------------------------------------------===//
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@ -226,58 +226,58 @@ let Defs = [SRW] in {
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let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
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// FIXME: Provide proper encoding!
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def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"add.b\t{$src2, $dst|$dst, $src2}",
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"add.b\t{$src2, $dst}",
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[(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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"add.w\t{$src2, $dst}",
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[(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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}
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def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"add.b\t{$src2, $dst|$dst, $src2}",
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"add.b\t{$src2, $dst}",
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[(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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"add.w\t{$src2, $dst}",
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[(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"add.b\t{$src2, $dst|$dst, $src2}",
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"add.b\t{$src2, $dst}",
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[(set GR8:$dst, (add GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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"add.w\t{$src2, $dst}",
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[(set GR16:$dst, (add GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"add.b\t{$src, $dst|$dst, $src}",
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"add.b\t{$src, $dst}",
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[(store (add (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"add.w\t{$src, $dst|$dst, $src}",
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"add.w\t{$src, $dst}",
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[(store (add (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"add.b\t{$src, $dst|$dst, $src}",
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"add.b\t{$src, $dst}",
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[(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"add.w\t{$src, $dst|$dst, $src}",
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"add.w\t{$src, $dst}",
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[(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"add.b\t{$src, $dst|$dst, $src}",
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"add.b\t{$src, $dst}",
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[(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"add.w\t{$src, $dst|$dst, $src}",
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"add.w\t{$src, $dst}",
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[(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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@ -286,58 +286,58 @@ let Uses = [SRW] in {
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let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
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def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"addc.b\t{$src2, $dst|$dst, $src2}",
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"addc.b\t{$src2, $dst}",
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[(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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"addc.w\t{$src2, $dst}",
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[(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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} // isCommutable
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def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"addc.b\t{$src2, $dst|$dst, $src2}",
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"addc.b\t{$src2, $dst}",
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[(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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"addc.w\t{$src2, $dst}",
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[(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"addc.b\t{$src2, $dst|$dst, $src2}",
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"addc.b\t{$src2, $dst}",
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[(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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"addc.w\t{$src2, $dst}",
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[(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"addc.b\t{$src, $dst|$dst, $src}",
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"addc.b\t{$src, $dst}",
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[(store (adde (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"addc.w\t{$src, $dst|$dst, $src}",
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"addc.w\t{$src, $dst}",
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[(store (adde (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"addc.b\t{$src, $dst|$dst, $src}",
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"addc.b\t{$src, $dst}",
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[(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"addc.w\t{$src, $dst|$dst, $src}",
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"addc.w\t{$src, $dst}",
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[(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"addc.b\t{$src, $dst|$dst, $src}",
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"addc.b\t{$src, $dst}",
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[(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"addc.w\t{$src, $dst|$dst, $src}",
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"addc.w\t{$src, $dst}",
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[(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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@ -346,58 +346,58 @@ def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
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def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"and.b\t{$src2, $dst|$dst, $src2}",
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"and.b\t{$src2, $dst}",
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[(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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"and.w\t{$src2, $dst}",
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[(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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}
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def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"and.b\t{$src2, $dst|$dst, $src2}",
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"and.b\t{$src2, $dst}",
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[(set GR8:$dst, (and GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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"and.w\t{$src2, $dst}",
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[(set GR16:$dst, (and GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"and.b\t{$src2, $dst|$dst, $src2}",
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"and.b\t{$src2, $dst}",
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[(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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"and.w\t{$src2, $dst}",
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[(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"and.b\t{$src, $dst|$dst, $src}",
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"and.b\t{$src, $dst}",
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[(store (and (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"and.w\t{$src, $dst|$dst, $src}",
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"and.w\t{$src, $dst}",
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[(store (and (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"and.b\t{$src, $dst|$dst, $src}",
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"and.b\t{$src, $dst}",
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[(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"and.w\t{$src, $dst|$dst, $src}",
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"and.w\t{$src, $dst}",
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[(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"and.b\t{$src, $dst|$dst, $src}",
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"and.b\t{$src, $dst}",
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[(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"and.w\t{$src, $dst|$dst, $src}",
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"and.w\t{$src, $dst}",
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[(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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@ -405,172 +405,172 @@ def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
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def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"xor.b\t{$src2, $dst|$dst, $src2}",
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"xor.b\t{$src2, $dst}",
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[(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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"xor.w\t{$src2, $dst}",
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[(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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}
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def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"xor.b\t{$src2, $dst|$dst, $src2}",
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"xor.b\t{$src2, $dst}",
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[(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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"xor.w\t{$src2, $dst}",
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[(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"xor.b\t{$src2, $dst|$dst, $src2}",
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"xor.b\t{$src2, $dst}",
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[(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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"xor.w\t{$src2, $dst}",
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[(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"xor.b\t{$src, $dst|$dst, $src}",
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"xor.b\t{$src, $dst}",
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[(store (xor (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"xor.w\t{$src, $dst|$dst, $src}",
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"xor.w\t{$src, $dst}",
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[(store (xor (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"xor.b\t{$src, $dst|$dst, $src}",
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"xor.b\t{$src, $dst}",
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[(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"xor.w\t{$src, $dst|$dst, $src}",
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"xor.w\t{$src, $dst}",
|
||||
[(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
|
||||
def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"xor.b\t{$src, $dst|$dst, $src}",
|
||||
"xor.b\t{$src, $dst}",
|
||||
[(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"xor.w\t{$src, $dst|$dst, $src}",
|
||||
"xor.w\t{$src, $dst}",
|
||||
[(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
}
|
||||
|
||||
|
||||
def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
||||
"sub.b\t{$src2, $dst|$dst, $src2}",
|
||||
"sub.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
|
||||
(implicit SRW)]>;
|
||||
def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
||||
"sub.w\t{$src2, $dst|$dst, $src2}",
|
||||
"sub.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
|
||||
(implicit SRW)]>;
|
||||
|
||||
def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
||||
"sub.b\t{$src2, $dst|$dst, $src2}",
|
||||
"sub.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
|
||||
"sub.w\t{$src2, $dst|$dst, $src2}",
|
||||
"sub.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
|
||||
def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
|
||||
"sub.b\t{$src2, $dst|$dst, $src2}",
|
||||
"sub.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
|
||||
"sub.w\t{$src2, $dst|$dst, $src2}",
|
||||
"sub.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
|
||||
let isTwoAddress = 0 in {
|
||||
def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
|
||||
"sub.b\t{$src, $dst|$dst, $src}",
|
||||
"sub.b\t{$src, $dst}",
|
||||
[(store (sub (load addr:$dst), GR8:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
|
||||
"sub.w\t{$src, $dst|$dst, $src}",
|
||||
"sub.w\t{$src, $dst}",
|
||||
[(store (sub (load addr:$dst), GR16:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
|
||||
def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
|
||||
"sub.b\t{$src, $dst|$dst, $src}",
|
||||
"sub.b\t{$src, $dst}",
|
||||
[(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
|
||||
"sub.w\t{$src, $dst|$dst, $src}",
|
||||
"sub.w\t{$src, $dst}",
|
||||
[(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
|
||||
def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"sub.b\t{$src, $dst|$dst, $src}",
|
||||
"sub.b\t{$src, $dst}",
|
||||
[(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"sub.w\t{$src, $dst|$dst, $src}",
|
||||
"sub.w\t{$src, $dst}",
|
||||
[(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
}
|
||||
|
||||
let Uses = [SRW] in {
|
||||
def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
||||
"subc.b\t{$src2, $dst|$dst, $src2}",
|
||||
"subc.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
|
||||
(implicit SRW)]>;
|
||||
def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
||||
"subc.w\t{$src2, $dst|$dst, $src2}",
|
||||
"subc.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
|
||||
(implicit SRW)]>;
|
||||
|
||||
def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
||||
"subc.b\t{$src2, $dst|$dst, $src2}",
|
||||
"subc.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
|
||||
"subc.w\t{$src2, $dst|$dst, $src2}",
|
||||
"subc.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
|
||||
def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
|
||||
"subc.b\t{$src2, $dst|$dst, $src2}",
|
||||
"subc.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
|
||||
"subc.w\t{$src2, $dst|$dst, $src2}",
|
||||
"subc.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
|
||||
let isTwoAddress = 0 in {
|
||||
def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
|
||||
"subc.b\t{$src, $dst|$dst, $src}",
|
||||
"subc.b\t{$src, $dst}",
|
||||
[(store (sube (load addr:$dst), GR8:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
|
||||
"subc.w\t{$src, $dst|$dst, $src}",
|
||||
"subc.w\t{$src, $dst}",
|
||||
[(store (sube (load addr:$dst), GR16:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
|
||||
def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
|
||||
"subc.b\t{$src, $dst|$dst, $src}",
|
||||
"subc.b\t{$src, $dst}",
|
||||
[(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
|
||||
"subc.w\t{$src, $dst|$dst, $src}",
|
||||
"subc.w\t{$src, $dst}",
|
||||
[(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
|
||||
def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"subc.b\t{$src, $dst|$dst, $src}",
|
||||
"subc.b\t{$src, $dst}",
|
||||
[(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"subc.w\t{$src, $dst|$dst, $src}",
|
||||
"subc.w\t{$src, $dst}",
|
||||
[(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
}
|
||||
|
|
@ -597,52 +597,52 @@ def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
|
|||
|
||||
let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
|
||||
def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
||||
"bis.b\t{$src2, $dst|$dst, $src2}",
|
||||
"bis.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
|
||||
def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
||||
"bis.w\t{$src2, $dst|$dst, $src2}",
|
||||
"bis.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
|
||||
}
|
||||
|
||||
def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
||||
"bis.b\t{$src2, $dst|$dst, $src2}",
|
||||
"bis.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
|
||||
def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
|
||||
"bis.w\t{$src2, $dst|$dst, $src2}",
|
||||
"bis.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
|
||||
|
||||
def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
|
||||
"bis.b\t{$src2, $dst|$dst, $src2}",
|
||||
"bis.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
|
||||
def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
|
||||
"bis.w\t{$src2, $dst|$dst, $src2}",
|
||||
"bis.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
|
||||
|
||||
let isTwoAddress = 0 in {
|
||||
def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
|
||||
"bis.b\t{$src, $dst|$dst, $src}",
|
||||
"bis.b\t{$src, $dst}",
|
||||
[(store (or (load addr:$dst), GR8:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
|
||||
"bis.w\t{$src, $dst|$dst, $src}",
|
||||
"bis.w\t{$src, $dst}",
|
||||
[(store (or (load addr:$dst), GR16:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
|
||||
def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
|
||||
"bis.b\t{$src, $dst|$dst, $src}",
|
||||
"bis.b\t{$src, $dst}",
|
||||
[(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
|
||||
"bis.w\t{$src, $dst|$dst, $src}",
|
||||
"bis.w\t{$src, $dst}",
|
||||
[(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
|
||||
def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"bis.b\t{$src, $dst|$dst, $src}",
|
||||
"bis.b\t{$src, $dst}",
|
||||
[(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"bis.w\t{$src, $dst|$dst, $src}",
|
||||
"bis.w\t{$src, $dst}",
|
||||
[(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
}
|
||||
|
|
@ -666,31 +666,31 @@ def CMP16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2),
|
|||
[(MSP430cmp GR16:$src1, imm:$src2), (implicit SRW)]>;
|
||||
|
||||
def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
|
||||
"cmp.b\t{$src2, $src1|$src1, $src2}",
|
||||
"cmp.b\t{$src1, $src2}",
|
||||
[(MSP430cmp GR8:$src1, (load addr:$src2)), (implicit SRW)]>;
|
||||
def CMP16rm : Pseudo<(outs), (ins GR16:$src1, memsrc:$src2),
|
||||
"cmp.w\t{$src2, $src1|$src1, $src2}",
|
||||
"cmp.w\t{$src1, $src2}",
|
||||
[(MSP430cmp GR16:$src1, (load addr:$src2)), (implicit SRW)]>;
|
||||
|
||||
def CMP8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2),
|
||||
"cmp.b\t{$src2, $src1|$src1, $src2}",
|
||||
"cmp.b\t{$src1, $src2}",
|
||||
[(MSP430cmp (load addr:$src1), GR8:$src2), (implicit SRW)]>;
|
||||
def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2),
|
||||
"cmp.w\t{$src2, $src1|$src1, $src2}",
|
||||
"cmp.w\t{$src1, $src2}",
|
||||
[(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>;
|
||||
|
||||
def CMP8mi : Pseudo<(outs), (ins memsrc:$src1, i8imm:$src2),
|
||||
"cmp.b\t{$src2, $src1|$src1, $src2}",
|
||||
"cmp.b\t{$src1, $src2}",
|
||||
[(MSP430cmp (load addr:$src1), (i8 imm:$src2)), (implicit SRW)]>;
|
||||
def CMP16mi : Pseudo<(outs), (ins memsrc:$src1, i16imm:$src2),
|
||||
"cmp.w\t{$src2, $src1|$src1, $src2}",
|
||||
"cmp.w\t{$src1, $src2}",
|
||||
[(MSP430cmp (load addr:$src1), (i16 imm:$src2)), (implicit SRW)]>;
|
||||
|
||||
def CMP8mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
|
||||
"cmp.b\t{$src2, $src1|$src1, $src2}",
|
||||
"cmp.b\t{$src1, $src2}",
|
||||
[(MSP430cmp (load addr:$src1), (i8 (load addr:$src2))), (implicit SRW)]>;
|
||||
def CMP16mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
|
||||
"cmp.w\t{$src2, $src1|$src1, $src2}",
|
||||
"cmp.w\t{$src1, $src2}",
|
||||
[(MSP430cmp (load addr:$src1), (i16 (load addr:$src2))), (implicit SRW)]>;
|
||||
} // Defs = [SRW]
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue