More DAG combining. Still need the branch instructions, and select_cc
llvm-svn: 23371
This commit is contained in:
Nate Begeman
parent
7884fffb00
commit
24a7eca282
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@ -100,9 +100,9 @@ namespace {
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SDOperand visitCTLZ(SDNode *N);
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SDOperand visitCTTZ(SDNode *N);
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SDOperand visitCTPOP(SDNode *N);
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// select
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// select_cc
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// setcc
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SDOperand visitSELECT(SDNode *N);
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SDOperand visitSELECT_CC(SDNode *N);
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SDOperand visitSETCC(SDNode *N);
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SDOperand visitSIGN_EXTEND(SDNode *N);
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SDOperand visitZERO_EXTEND(SDNode *N);
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SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
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@ -116,10 +116,13 @@ namespace {
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SDOperand visitFP_EXTEND(SDNode *N);
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SDOperand visitFNEG(SDNode *N);
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SDOperand visitFABS(SDNode *N);
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// brcond
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SDOperand visitBRCOND(SDNode *N);
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// brcondtwoway
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// br_cc
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// brtwoway_cc
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SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
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ISD::CondCode Cond);
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public:
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DAGCombiner(SelectionDAG &D)
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: DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
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@ -234,6 +237,19 @@ static bool isOneUseSetCC(SDOperand N) {
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return false;
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}
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// FIXME: This should probably go in the ISD class rather than being duplicated
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// in several files.
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static bool isCommutativeBinOp(unsigned Opcode) {
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switch (Opcode) {
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case ISD::ADD:
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case ISD::MUL:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR: return true;
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default: return false; // FIXME: Need commutative info for user ops!
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}
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}
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void DAGCombiner::Run(bool RunningAfterLegalize) {
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// set the instance variable, so that the various visit routines may use it.
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AfterLegalize = RunningAfterLegalize;
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@ -307,6 +323,9 @@ SDOperand DAGCombiner::visit(SDNode *N) {
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case ISD::CTLZ: return visitCTLZ(N);
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case ISD::CTTZ: return visitCTTZ(N);
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case ISD::CTPOP: return visitCTPOP(N);
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case ISD::SELECT: return visitSELECT(N);
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case ISD::SELECT_CC: return visitSELECT_CC(N);
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case ISD::SETCC: return visitSETCC(N);
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case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
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case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
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case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
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@ -669,6 +688,15 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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WorkList.push_back(ANDNode.Val);
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return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
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}
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// fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
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if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
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(N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
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N0.getOperand(1) == N1.getOperand(1)) {
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SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
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N0.getOperand(0), N1.getOperand(0));
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WorkList.push_back(ANDNode.Val);
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return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
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}
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return SDOperand();
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}
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@ -993,6 +1021,63 @@ SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
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return SDOperand();
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}
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SDOperand DAGCombiner::visitSELECT(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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SDOperand N2 = N->getOperand(2);
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ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
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MVT::ValueType VT = N->getValueType(0);
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// fold select C, X, X -> X
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if (N1 == N2)
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return N1;
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// fold select true, X, Y -> X
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if (N0C && !N0C->isNullValue())
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return N1;
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// fold select false, X, Y -> Y
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if (N0C && N0C->isNullValue())
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return N2;
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// fold select C, 1, X -> C | X
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if (MVT::i1 == VT && N1C && !N1C->isNullValue())
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return DAG.getNode(ISD::OR, VT, N0, N2);
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// fold select C, 0, X -> ~C & X
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// FIXME: this should check for C type == X type, not i1?
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if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
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SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
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WorkList.push_back(XORNode.Val);
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return DAG.getNode(ISD::AND, VT, XORNode, N2);
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}
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// fold select C, X, 1 -> ~C | X
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if (MVT::i1 == VT && N2C && !N2C->isNullValue()) {
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SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
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WorkList.push_back(XORNode.Val);
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return DAG.getNode(ISD::OR, VT, XORNode, N1);
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}
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// fold select C, X, 0 -> C & X
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// FIXME: this should check for C type == X type, not i1?
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if (MVT::i1 == VT && N2C && N2C->isNullValue())
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return DAG.getNode(ISD::AND, VT, N0, N1);
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// fold X ? X : Y --> X ? 1 : Y --> X | Y
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if (MVT::i1 == VT && N0 == N1)
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return DAG.getNode(ISD::OR, VT, N0, N2);
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// fold X ? Y : X --> X ? Y : 0 --> X & Y
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if (MVT::i1 == VT && N0 == N2)
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return DAG.getNode(ISD::AND, VT, N0, N1);
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return SDOperand();
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}
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SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
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return SDOperand();
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}
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SDOperand DAGCombiner::visitSETCC(SDNode *N) {
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return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
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cast<CondCodeSDNode>(N->getOperand(2))->get());
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}
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SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
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@ -1024,7 +1109,6 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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SDOperand LHS, RHS, CC;
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ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
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MVT::ValueType VT = N->getValueType(0);
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MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
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@ -1206,6 +1290,342 @@ SDOperand DAGCombiner::visitFABS(SDNode *N) {
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return SDOperand();
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}
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SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
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SDOperand N1, ISD::CondCode Cond) {
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// These setcc operations always fold.
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switch (Cond) {
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default: break;
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case ISD::SETFALSE:
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case ISD::SETFALSE2: return DAG.getConstant(0, VT);
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case ISD::SETTRUE:
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case ISD::SETTRUE2: return DAG.getConstant(1, VT);
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}
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if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
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uint64_t C1 = N1C->getValue();
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if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
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uint64_t C0 = N0C->getValue();
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// Sign extend the operands if required
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if (ISD::isSignedIntSetCC(Cond)) {
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C0 = N0C->getSignExtended();
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C1 = N1C->getSignExtended();
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}
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switch (Cond) {
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default: assert(0 && "Unknown integer setcc!");
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case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
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case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
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case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
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case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
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case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
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case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
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case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
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case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
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case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
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case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
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}
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} else {
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// If the LHS is a ZERO_EXTEND, perform the comparison on the input.
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if (N0.getOpcode() == ISD::ZERO_EXTEND) {
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unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
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// If the comparison constant has bits in the upper part, the
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// zero-extended value could never match.
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if (C1 & (~0ULL << InSize)) {
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unsigned VSize = MVT::getSizeInBits(N0.getValueType());
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switch (Cond) {
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case ISD::SETUGT:
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case ISD::SETUGE:
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case ISD::SETEQ: return DAG.getConstant(0, VT);
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case ISD::SETULT:
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case ISD::SETULE:
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case ISD::SETNE: return DAG.getConstant(1, VT);
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case ISD::SETGT:
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case ISD::SETGE:
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// True if the sign bit of C1 is set.
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return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
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case ISD::SETLT:
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case ISD::SETLE:
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// True if the sign bit of C1 isn't set.
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return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
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default:
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break;
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}
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}
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// Otherwise, we can perform the comparison with the low bits.
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switch (Cond) {
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case ISD::SETEQ:
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case ISD::SETNE:
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case ISD::SETUGT:
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case ISD::SETUGE:
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case ISD::SETULT:
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case ISD::SETULE:
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return DAG.getSetCC(VT, N0.getOperand(0),
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DAG.getConstant(C1, N0.getOperand(0).getValueType()),
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Cond);
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default:
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break; // todo, be more careful with signed comparisons
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}
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} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
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(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
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MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
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unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
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MVT::ValueType ExtDstTy = N0.getValueType();
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unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
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// If the extended part has any inconsistent bits, it cannot ever
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// compare equal. In other words, they have to be all ones or all
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// zeros.
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uint64_t ExtBits =
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(~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
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if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
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return DAG.getConstant(Cond == ISD::SETNE, VT);
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SDOperand ZextOp;
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MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
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if (Op0Ty == ExtSrcTy) {
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ZextOp = N0.getOperand(0);
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} else {
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int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
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ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
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DAG.getConstant(Imm, Op0Ty));
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}
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WorkList.push_back(ZextOp.Val);
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// Otherwise, make this a use of a zext.
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return DAG.getSetCC(VT, ZextOp,
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DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
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ExtDstTy),
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Cond);
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}
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uint64_t MinVal, MaxVal;
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unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
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if (ISD::isSignedIntSetCC(Cond)) {
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MinVal = 1ULL << (OperandBitSize-1);
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if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
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MaxVal = ~0ULL >> (65-OperandBitSize);
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else
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MaxVal = 0;
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} else {
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MinVal = 0;
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MaxVal = ~0ULL >> (64-OperandBitSize);
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}
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// Canonicalize GE/LE comparisons to use GT/LT comparisons.
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if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
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if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
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--C1; // X >= C0 --> X > (C0-1)
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return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
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(Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
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}
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if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
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if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
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++C1; // X <= C0 --> X < (C0+1)
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return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
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(Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
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}
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if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
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return DAG.getConstant(0, VT); // X < MIN --> false
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// Canonicalize setgt X, Min --> setne X, Min
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if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
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return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
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// If we have setult X, 1, turn it into seteq X, 0
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if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
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return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
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ISD::SETEQ);
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// If we have setugt X, Max-1, turn it into seteq X, Max
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else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
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return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
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ISD::SETEQ);
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// If we have "setcc X, C0", check to see if we can shrink the immediate
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// by changing cc.
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// SETUGT X, SINTMAX -> SETLT X, 0
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if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
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C1 == (~0ULL >> (65-OperandBitSize)))
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return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
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ISD::SETLT);
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// FIXME: Implement the rest of these.
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// Fold bit comparisons when we can.
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if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
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VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
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if (ConstantSDNode *AndRHS =
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dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
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if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
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// Perform the xform if the AND RHS is a single bit.
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if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
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return DAG.getNode(ISD::SRL, VT, N0,
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DAG.getConstant(Log2_64(AndRHS->getValue()),
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TLI.getShiftAmountTy()));
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}
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} else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
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// (X & 8) == 8 --> (X & 8) >> 3
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// Perform the xform if C1 is a single bit.
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if ((C1 & (C1-1)) == 0) {
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return DAG.getNode(ISD::SRL, VT, N0,
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DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
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}
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}
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}
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}
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} else if (isa<ConstantSDNode>(N0.Val)) {
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// Ensure that the constant occurs on the RHS.
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return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
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}
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if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
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if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
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double C0 = N0C->getValue(), C1 = N1C->getValue();
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switch (Cond) {
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default: break; // FIXME: Implement the rest of these!
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case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
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case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
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case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
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case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
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case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
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case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
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}
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} else {
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// Ensure that the constant occurs on the RHS.
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return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
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}
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if (N0 == N1) {
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// We can always fold X == Y for integer setcc's.
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if (MVT::isInteger(N0.getValueType()))
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return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
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unsigned UOF = ISD::getUnorderedFlavor(Cond);
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if (UOF == 2) // FP operators that are undefined on NaNs.
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return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
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if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
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return DAG.getConstant(UOF, VT);
|
||||
// Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
|
||||
// if it is not already.
|
||||
ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO;
|
||||
if (NewCond != Cond)
|
||||
return DAG.getSetCC(VT, N0, N1, NewCond);
|
||||
}
|
||||
|
||||
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
|
||||
MVT::isInteger(N0.getValueType())) {
|
||||
if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
|
||||
N0.getOpcode() == ISD::XOR) {
|
||||
// Simplify (X+Y) == (X+Z) --> Y == Z
|
||||
if (N0.getOpcode() == N1.getOpcode()) {
|
||||
if (N0.getOperand(0) == N1.getOperand(0))
|
||||
return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
|
||||
if (N0.getOperand(1) == N1.getOperand(1))
|
||||
return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
|
||||
if (isCommutativeBinOp(N0.getOpcode())) {
|
||||
// If X op Y == Y op X, try other combinations.
|
||||
if (N0.getOperand(0) == N1.getOperand(1))
|
||||
return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
|
||||
if (N0.getOperand(1) == N1.getOperand(0))
|
||||
return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
|
||||
}
|
||||
}
|
||||
|
||||
// Simplify (X+Z) == X --> Z == 0
|
||||
if (N0.getOperand(0) == N1)
|
||||
return DAG.getSetCC(VT, N0.getOperand(1),
|
||||
DAG.getConstant(0, N0.getValueType()), Cond);
|
||||
if (N0.getOperand(1) == N1) {
|
||||
if (isCommutativeBinOp(N0.getOpcode()))
|
||||
return DAG.getSetCC(VT, N0.getOperand(0),
|
||||
DAG.getConstant(0, N0.getValueType()), Cond);
|
||||
else {
|
||||
assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
|
||||
// (Z-X) == X --> Z == X<<1
|
||||
SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
|
||||
N1,
|
||||
DAG.getConstant(1,TLI.getShiftAmountTy()));
|
||||
WorkList.push_back(SH.Val);
|
||||
return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
|
||||
N1.getOpcode() == ISD::XOR) {
|
||||
// Simplify X == (X+Z) --> Z == 0
|
||||
if (N1.getOperand(0) == N0) {
|
||||
return DAG.getSetCC(VT, N1.getOperand(1),
|
||||
DAG.getConstant(0, N1.getValueType()), Cond);
|
||||
} else if (N1.getOperand(1) == N0) {
|
||||
if (isCommutativeBinOp(N1.getOpcode())) {
|
||||
return DAG.getSetCC(VT, N1.getOperand(0),
|
||||
DAG.getConstant(0, N1.getValueType()), Cond);
|
||||
} else {
|
||||
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
|
||||
// X == (Z-X) --> X<<1 == Z
|
||||
SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
|
||||
DAG.getConstant(1,TLI.getShiftAmountTy()));
|
||||
WorkList.push_back(SH.Val);
|
||||
return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Fold away ALL boolean setcc's.
|
||||
SDOperand Temp;
|
||||
if (N0.getValueType() == MVT::i1) {
|
||||
switch (Cond) {
|
||||
default: assert(0 && "Unknown integer setcc!");
|
||||
case ISD::SETEQ: // X == Y -> (X^Y)^1
|
||||
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
|
||||
N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
|
||||
WorkList.push_back(Temp.Val);
|
||||
break;
|
||||
case ISD::SETNE: // X != Y --> (X^Y)
|
||||
N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
|
||||
break;
|
||||
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
|
||||
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
|
||||
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
|
||||
N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
|
||||
WorkList.push_back(Temp.Val);
|
||||
break;
|
||||
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
|
||||
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
|
||||
Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
|
||||
N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
|
||||
WorkList.push_back(Temp.Val);
|
||||
break;
|
||||
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
|
||||
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
|
||||
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
|
||||
N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
|
||||
WorkList.push_back(Temp.Val);
|
||||
break;
|
||||
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
|
||||
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
|
||||
Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
|
||||
N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
|
||||
break;
|
||||
}
|
||||
if (VT != MVT::i1) {
|
||||
WorkList.push_back(N0.Val);
|
||||
// FIXME: If running after legalize, we probably can't do this.
|
||||
N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
|
||||
}
|
||||
return N0;
|
||||
}
|
||||
|
||||
// Could not fold it.
|
||||
return SDOperand();
|
||||
}
|
||||
|
||||
// SelectionDAG::Combine - This is the entry point for the file.
|
||||
//
|
||||
void SelectionDAG::Combine(bool RunningAfterLegalize) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue