This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.
llvm-svn: 184716
This commit is contained in:
Vladimir Medic
parent
f989929cf0
commit
233dd51b13
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@ -104,6 +104,15 @@ class MipsAsmParser : public MCTargetAsmParser {
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MipsAsmParser::OperandMatchResultTy
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parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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MipsAsmParser::OperandMatchResultTy
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parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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MipsAsmParser::OperandMatchResultTy
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parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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MipsAsmParser::OperandMatchResultTy
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parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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unsigned RegKind);
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@ -177,8 +186,6 @@ class MipsAsmParser : public MCTargetAsmParser {
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FpFormatTy getFpFormat() {return FpFormat;}
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bool requestsDoubleOperand(StringRef Mnemonic);
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unsigned getReg(int RC, int RegNo);
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int getATReg();
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@ -385,6 +392,18 @@ public:
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return Reg.Kind == Kind_CCRRegs;
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}
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bool isAFGR64Asm() const {
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return Kind == k_Register && Reg.Kind == Kind_AFGR64Regs;
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}
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bool isFGR64Asm() const {
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return Kind == k_Register && Reg.Kind == Kind_FGR64Regs;
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}
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bool isFGR32Asm() const {
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return (Kind == k_Register) && Reg.Kind == Kind_FGR32Regs;
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}
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const {
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return StartLoc;
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@ -838,18 +857,6 @@ void MipsAsmParser::setDefaultFpFormat() {
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FpFormat = FP_FORMAT_S;
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}
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bool MipsAsmParser::requestsDoubleOperand(StringRef Mnemonic){
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bool IsDouble = StringSwitch<bool>(Mnemonic.lower())
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.Case("ldxc1", true)
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.Case("ldc1", true)
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.Case("sdxc1", true)
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.Case("sdc1", true)
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.Default(false);
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return IsDouble;
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}
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void MipsAsmParser::setFpFormat(StringRef Format) {
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FpFormat = StringSwitch<FpFormatTy>(Format.lower())
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@ -1280,6 +1287,34 @@ MipsAsmParser::parseCPURegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseRegs(Operands, (int) MipsOperand::Kind_CPURegs);
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}
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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if (isFP64())
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return MatchOperand_NoMatch;
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// Double operand is expected, set appropriate format
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setFpFormat(FP_FORMAT_D);
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return parseRegs(Operands, (int) MipsOperand::Kind_AFGR64Regs);
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}
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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if (!isFP64())
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return MatchOperand_NoMatch;
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// Double operand is expected, set appropriate format
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setFpFormat(FP_FORMAT_D);
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return parseRegs(Operands, (int) MipsOperand::Kind_FGR64Regs);
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}
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// Single operand is expected, set appropriate format
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setFpFormat(FP_FORMAT_S);
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return parseRegs(Operands, (int) MipsOperand::Kind_FGR32Regs);
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}
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bool MipsAsmParser::searchSymbolAlias(
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SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind) {
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@ -1537,50 +1572,44 @@ bool MipsAsmParser::
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ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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StringRef Mnemonic;
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// Floating point instructions: Should the register be treated as a double?
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if (requestsDoubleOperand(Name)) {
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setFpFormat(FP_FORMAT_D);
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Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
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Mnemonic = Name;
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} else {
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setDefaultFpFormat();
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// Create the leading tokens for the mnemonic, split by '.' characters.
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size_t Start = 0, Next = Name.find('.');
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Mnemonic = Name.slice(Start, Next);
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Operands.push_back(MipsOperand::CreateToken(Mnemonic, NameLoc));
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setDefaultFpFormat();
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// Create the leading tokens for the mnemonic, split by '.' characters.
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size_t Start = 0, Next = Name.find('.');
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Mnemonic = Name.slice(Start, Next);
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if (Next != StringRef::npos) {
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// There is a format token in mnemonic.
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size_t Dot = Name.find('.', Next + 1);
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StringRef Format = Name.slice(Next, Dot);
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if (Dot == StringRef::npos) // Only one '.' in a string, it's a format.
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Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
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else {
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if (Name.startswith("c.")) {
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// Floating point compare, add '.' and immediate represent for cc.
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Operands.push_back(MipsOperand::CreateToken(".", NameLoc));
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int Cc = ConvertCcString(Format);
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if (Cc == -1) {
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return Error(NameLoc, "Invalid conditional code");
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}
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SMLoc E = SMLoc::getFromPointer(
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Parser.getTok().getLoc().getPointer() - 1);
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Operands.push_back(
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MipsOperand::CreateImm(MCConstantExpr::Create(Cc, getContext()),
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NameLoc, E));
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} else {
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// trunc, ceil, floor ...
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return parseMathOperation(Name, NameLoc, Operands);
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Operands.push_back(MipsOperand::CreateToken(Mnemonic, NameLoc));
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if (Next != StringRef::npos) {
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// There is a format token in mnemonic.
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size_t Dot = Name.find('.', Next + 1);
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StringRef Format = Name.slice(Next, Dot);
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if (Dot == StringRef::npos) // Only one '.' in a string, it's a format.
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Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
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else {
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if (Name.startswith("c.")) {
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// Floating point compare, add '.' and immediate represent for cc.
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Operands.push_back(MipsOperand::CreateToken(".", NameLoc));
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int Cc = ConvertCcString(Format);
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if (Cc == -1) {
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return Error(NameLoc, "Invalid conditional code");
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}
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// The rest is a format.
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Format = Name.slice(Dot, StringRef::npos);
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Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
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SMLoc E = SMLoc::getFromPointer(
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Parser.getTok().getLoc().getPointer() - 1);
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Operands.push_back(
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MipsOperand::CreateImm(MCConstantExpr::Create(Cc, getContext()),
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NameLoc, E));
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} else {
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// trunc, ceil, floor ...
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return parseMathOperation(Name, NameLoc, Operands);
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}
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setFpFormat(Format);
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// The rest is a format.
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Format = Name.slice(Dot, StringRef::npos);
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Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
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}
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setFpFormat(Format);
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}
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// Read the remaining operands.
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@ -151,7 +151,7 @@ class MTC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterClass SrcRC,
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InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
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[(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
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class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
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class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> {
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@ -159,7 +159,7 @@ class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
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let mayLoad = 1;
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}
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class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
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class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> {
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@ -180,7 +180,7 @@ class NMADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
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[(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
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Itin, FrmFR>;
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class LWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
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class LWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
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InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
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InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
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!strconcat(opstr, "\t$fd, ${index}(${base})"),
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@ -188,7 +188,7 @@ class LWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
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let AddedComplexity = 20;
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}
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class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
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class SWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
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InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
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InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
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!strconcat(opstr, "\t$fs, ${index}(${base})"),
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@ -304,73 +304,87 @@ def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
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/// Floating Point Memory Instructions
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let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
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def LWC1_P8 : LW_FT<"lwc1", FGR32, IILoad, mem64, load>, LW_FM<0x31>;
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def SWC1_P8 : SW_FT<"swc1", FGR32, IIStore, mem64, store>, LW_FM<0x39>;
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def LDC164_P8 : LW_FT<"ldc1", FGR64, IILoad, mem64, load>, LW_FM<0x35> {
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def LWC1_P8 : LW_FT<"lwc1", FGR32RegsOpnd, IILoad, mem64, load>, LW_FM<0x31>;
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def SWC1_P8 : SW_FT<"swc1", FGR32RegsOpnd, IIStore, mem64, store>,
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LW_FM<0x39>;
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def LDC164_P8 : LW_FT<"ldc1", FGR64RegsOpnd, IILoad, mem64, load>,
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LW_FM<0x35> {
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let isCodeGenOnly =1;
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}
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def SDC164_P8 : SW_FT<"sdc1", FGR64, IIStore, mem64, store>, LW_FM<0x3d> {
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def SDC164_P8 : SW_FT<"sdc1", FGR64RegsOpnd, IIStore, mem64, store>,
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LW_FM<0x3d> {
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let isCodeGenOnly =1;
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}
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}
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let Predicates = [NotN64, HasStdEnc] in {
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def LWC1 : LW_FT<"lwc1", FGR32, IILoad, mem, load>, LW_FM<0x31>;
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def SWC1 : SW_FT<"swc1", FGR32, IIStore, mem, store>, LW_FM<0x39>;
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def LWC1 : LW_FT<"lwc1", FGR32RegsOpnd, IILoad, mem, load>, LW_FM<0x31>;
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def SWC1 : SW_FT<"swc1", FGR32RegsOpnd, IIStore, mem, store>, LW_FM<0x39>;
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}
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let Predicates = [NotN64, HasMips64, HasStdEnc],
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DecoderNamespace = "Mips64" in {
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def LDC164 : LW_FT<"ldc1", FGR64, IILoad, mem, load>, LW_FM<0x35>;
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def SDC164 : SW_FT<"sdc1", FGR64, IIStore, mem, store>, LW_FM<0x3d>;
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def LDC164 : LW_FT<"ldc1", FGR64RegsOpnd, IILoad, mem, load>, LW_FM<0x35>;
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def SDC164 : SW_FT<"sdc1", FGR64RegsOpnd, IIStore, mem, store>, LW_FM<0x3d>;
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}
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let Predicates = [NotN64, NotMips64, HasStdEnc] in {
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let isPseudo = 1, isCodeGenOnly = 1 in {
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def PseudoLDC1 : LW_FT<"", AFGR64, IILoad, mem, load>;
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def PseudoSDC1 : SW_FT<"", AFGR64, IIStore, mem, store>;
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def PseudoLDC1 : LW_FT<"", AFGR64RegsOpnd, IILoad, mem, load>;
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def PseudoSDC1 : SW_FT<"", AFGR64RegsOpnd, IIStore, mem, store>;
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}
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def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem>, LW_FM<0x35>;
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def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem>, LW_FM<0x3d>;
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def LDC1 : LW_FT<"ldc1", AFGR64RegsOpnd, IILoad, mem>, LW_FM<0x35>;
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def SDC1 : SW_FT<"sdc1", AFGR64RegsOpnd, IIStore, mem>, LW_FM<0x3d>;
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}
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// Indexed loads and stores.
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let Predicates = [HasFPIdx, HasStdEnc] in {
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def LWXC1 : LWXC1_FT<"lwxc1", FGR32, CPURegs, IILoad, load>, LWXC1_FM<0>;
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def SWXC1 : SWXC1_FT<"swxc1", FGR32, CPURegs, IIStore, store>, SWXC1_FM<8>;
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def LWXC1 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPURegsOpnd, IILoad, load>,
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LWXC1_FM<0>;
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def SWXC1 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPURegsOpnd, IIStore, store>,
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SWXC1_FM<8>;
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}
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let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
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def LDXC1 : LWXC1_FT<"ldxc1", AFGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
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def SDXC1 : SWXC1_FT<"sdxc1", AFGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
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def LDXC1 : LWXC1_FT<"ldxc1", AFGR64RegsOpnd, CPURegsOpnd, IILoad, load>,
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LWXC1_FM<1>;
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def SDXC1 : SWXC1_FT<"sdxc1", AFGR64RegsOpnd, CPURegsOpnd, IIStore, store>,
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SWXC1_FM<9>;
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}
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let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
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def LDXC164 : LWXC1_FT<"ldxc1", FGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
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def SDXC164 : SWXC1_FT<"sdxc1", FGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
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def LDXC164 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPURegsOpnd, IILoad, load>,
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LWXC1_FM<1>;
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def SDXC164 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPURegsOpnd, IIStore, store>,
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SWXC1_FM<9>;
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}
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// n64
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let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
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def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32, CPU64Regs, IILoad, load>, LWXC1_FM<0>;
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def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64, CPU64Regs, IILoad, load>,
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LWXC1_FM<1>;
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def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32, CPU64Regs, IIStore, store>,
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SWXC1_FM<8>;
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def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64, CPU64Regs, IIStore, store>,
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SWXC1_FM<9>;
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def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPU64RegsOpnd, IILoad, load>,
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LWXC1_FM<0>;
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def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPU64RegsOpnd, IILoad,
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load>, LWXC1_FM<1>;
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def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIStore,
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store>, SWXC1_FM<8>;
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def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIStore,
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store>, SWXC1_FM<9>;
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}
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// Load/store doubleword indexed unaligned.
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let Predicates = [NotMips64, HasStdEnc] in {
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def LUXC1 : LWXC1_FT<"luxc1", AFGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
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def SUXC1 : SWXC1_FT<"suxc1", AFGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
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def LUXC1 : LWXC1_FT<"luxc1", AFGR64RegsOpnd, CPURegsOpnd, IILoad>,
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LWXC1_FM<0x5>;
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def SUXC1 : SWXC1_FT<"suxc1", AFGR64RegsOpnd, CPURegsOpnd, IIStore>,
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SWXC1_FM<0xd>;
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}
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let Predicates = [HasMips64, HasStdEnc],
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DecoderNamespace="Mips64" in {
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def LUXC164 : LWXC1_FT<"luxc1", FGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
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def SUXC164 : SWXC1_FT<"suxc1", FGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
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def LUXC164 : LWXC1_FT<"luxc1", FGR64RegsOpnd, CPURegsOpnd, IILoad>,
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LWXC1_FM<0x5>;
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def SUXC164 : SWXC1_FT<"suxc1", FGR64RegsOpnd, CPURegsOpnd, IIStore>,
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SWXC1_FM<0xd>;
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}
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/// Floating-point Aritmetic
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@ -407,6 +407,21 @@ def CCRAsmOperand : MipsAsmRegOperand {
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let ParserMethod = "parseCCRRegs";
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}
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def AFGR64AsmOperand : MipsAsmRegOperand {
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let Name = "AFGR64Asm";
|
||||
let ParserMethod = "parseAFGR64Regs";
|
||||
}
|
||||
|
||||
def FGR64AsmOperand : MipsAsmRegOperand {
|
||||
let Name = "FGR64Asm";
|
||||
let ParserMethod = "parseFGR64Regs";
|
||||
}
|
||||
|
||||
def FGR32AsmOperand : MipsAsmRegOperand {
|
||||
let Name = "FGR32Asm";
|
||||
let ParserMethod = "parseFGR32Regs";
|
||||
}
|
||||
|
||||
def CPURegsOpnd : RegisterOperand<CPURegs, "printCPURegs"> {
|
||||
let ParserMatchClass = CPURegsAsmOperand;
|
||||
}
|
||||
|
|
@ -436,3 +451,15 @@ def HWRegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
|
|||
def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> {
|
||||
let ParserMatchClass = HW64RegsAsmOperand;
|
||||
}
|
||||
|
||||
def AFGR64RegsOpnd : RegisterOperand<AFGR64> {
|
||||
let ParserMatchClass = AFGR64AsmOperand;
|
||||
}
|
||||
|
||||
def FGR64RegsOpnd : RegisterOperand<FGR64> {
|
||||
let ParserMatchClass = FGR64AsmOperand;
|
||||
}
|
||||
|
||||
def FGR32RegsOpnd : RegisterOperand<FGR32> {
|
||||
let ParserMatchClass = FGR32AsmOperand;
|
||||
}
|
||||
Loading…
Reference in New Issue